From patchwork Thu Oct 8 09:26:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 317468 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1171877ilm; Thu, 8 Oct 2020 02:30:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9YD3+w0/pClUdmRxNR3MiP/kv7SAebGmYbtCX3yLdhT9VebrTWHkvpmq9oyUPeKIcV2zR X-Received: by 2002:a17:906:53d7:: with SMTP id p23mr7590361ejo.232.1602149430701; Thu, 08 Oct 2020 02:30:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602149430; cv=none; d=google.com; s=arc-20160816; b=hwwv6kwn64G3T7gC1eCR6bKIiPd6K503pyZLHgpj+4N1ojOpaktOqiuw58Bul6ow7H qYSTHRZOCM+rssdcO80OFlgQ+UW4OKhayi5VLhSRfhFFFJsYfSKjCkbNsDdaN3X4cg8S 55hvpufpdiulExm+R7bKAhB/9Jj0GRtcFJrOU23zD6dfN+kgwvaNxqiwu9E8rmzW/viP lL94WzHsMJnp7K0oCtqbWHbR5wFwX5+sx73xa7ZF0+P+a4AO+q+9u5dItEHwEKi4GzGY ES09vNMsY1iTFUbRSoFebuVv/o/iGAeVmzDo0JvNhdzl4CTLH0Yj5XZ0ntx92FqbJUvA 913Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=DkQffVzRy1LiNuA9+PqZ+X/O/xD5DmZ+GFLk4/pgH4k=; b=xx03MugKdRvll8TNpec52FgaX5+0OLKQ434q1rjVZwdKPIhV7amUQE4M4v4j7MVCpU 8IvL4pfFTzKKA014D2dGqtcqIzj2GFnfzByPj2jRduKyY8FXfkUkCZ7vRsejCAbGeFXt RJXKk3JlvqGHWRFCU21IlsiymReouxj+cFx/gLkCCvalKQyQ8OZBtgWLQjUSsGsbbY2C ytlPO6qlto4MkLXGMQj+06b6TEHawq18legmma6nYW3E8SxJBTcrhwimazd2T5aJq3uo LvBu5R1kiXh7RQFogPkvu6A3wkJsHwtDtbVPiXSjiHfRDhfvnr+FNVcL/ahiqjVHdBKw JvgQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c93si3155656edf.452.2020.10.08.02.30.30; Thu, 08 Oct 2020 02:30:30 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728996AbgJHJaS (ORCPT + 6 others); Thu, 8 Oct 2020 05:30:18 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:35156 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726273AbgJHJaR (ORCPT ); Thu, 8 Oct 2020 05:30:17 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 4D36BE57EAAFBFC61C40; Thu, 8 Oct 2020 17:30:14 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Thu, 8 Oct 2020 17:30:05 +0800 From: John Garry To: , , , , , CC: , , , , , , , John Garry Subject: [PATCH v2 3/4] perf/imx_ddr: Add system PMU identifier for userspace Date: Thu, 8 Oct 2020 17:26:20 +0800 Message-ID: <1602149181-237415-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1602149181-237415-1-git-send-email-john.garry@huawei.com> References: <1602149181-237415-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Joakim Zhang The DDR Perf for i.MX8 is a system PMU whose AXI ID would different from SoC to SoC. Need expose system PMU identifier for userspace which refer to /sys/bus/event_source/devices//identifier. Reviewed-by: John Garry Signed-off-by: Joakim Zhang Signed-off-by: John Garry --- drivers/perf/fsl_imx8_ddr_perf.c | 45 +++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) -- 2.26.2 diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 397540a4b799..c537cd9b8142 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -50,21 +50,38 @@ static DEFINE_IDA(ddr_ida); struct fsl_ddr_devtype_data { unsigned int quirks; /* quirks needed for different DDR Perf core */ + const char *identifier; /* system PMU identifier for userspace */ }; -static const struct fsl_ddr_devtype_data imx8_devtype_data; +static const struct fsl_ddr_devtype_data imx8_devtype_data = { + .identifier = "i.MX8", +}; + +static const struct fsl_ddr_devtype_data imx8mq_devtype_data = { + .quirks = DDR_CAP_AXI_ID_FILTER, + .identifier = "i.MX8MQ", +}; + +static const struct fsl_ddr_devtype_data imx8mm_devtype_data = { + .quirks = DDR_CAP_AXI_ID_FILTER, + .identifier = "i.MX8MM", +}; -static const struct fsl_ddr_devtype_data imx8m_devtype_data = { +static const struct fsl_ddr_devtype_data imx8mn_devtype_data = { .quirks = DDR_CAP_AXI_ID_FILTER, + .identifier = "i.MX8MN", }; static const struct fsl_ddr_devtype_data imx8mp_devtype_data = { .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED, + .identifier = "i.MX8MP", }; static const struct of_device_id imx_ddr_pmu_dt_ids[] = { { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data}, - { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data}, + { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data}, + { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data}, + { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data}, { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data}, { /* sentinel */ } }; @@ -84,6 +101,27 @@ struct ddr_pmu { int id; }; +static ssize_t ddr_perf_identifier_show(struct device *dev, + struct device_attribute *attr, + char *page) +{ + struct ddr_pmu *pmu = dev_get_drvdata(dev); + + return sprintf(page, "%s\n", pmu->devtype_data->identifier); +} + +static struct device_attribute ddr_perf_identifier_attr = + __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL); + +static struct attribute *ddr_perf_identifier_attrs[] = { + &ddr_perf_identifier_attr.attr, + NULL, +}; + +static struct attribute_group ddr_perf_identifier_attr_group = { + .attrs = ddr_perf_identifier_attrs, +}; + enum ddr_perf_filter_capabilities { PERF_CAP_AXI_ID_FILTER = 0, PERF_CAP_AXI_ID_FILTER_ENHANCED, @@ -237,6 +275,7 @@ static const struct attribute_group *attr_groups[] = { &ddr_perf_format_attr_group, &ddr_perf_cpumask_attr_group, &ddr_perf_filter_cap_attr_group, + &ddr_perf_identifier_attr_group, NULL, };