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Thu, 4 Feb 2021 05:53:39 -0800 Envelope-to: git-dev@xilinx.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, shubhrajyoti.datta@gmail.com, sboyd@kernel.org, robh+dt@kernel.org, gregkh@linuxfoundation.org Received: from [10.140.6.59] (port=57876 helo=xhdshubhraj40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l7f4j-0000Tm-7o; Thu, 04 Feb 2021 05:53:37 -0800 From: Shubhrajyoti Datta To: , CC: , , , , , Shubhrajyoti Datta Subject: [PATCH v8 1/7] dt-bindings: add documentation of xilinx clocking wizard Date: Thu, 4 Feb 2021 19:23:24 +0530 Message-ID: <1612446810-6113-2-git-send-email-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1612446810-6113-1-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1612446810-6113-1-git-send-email-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 97dd8ca8-da3b-47bd-0a8f-08d8c91452bc X-MS-TrafficTypeDiagnostic: DM6PR02MB5994: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:439; 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Signed-off-by: Shubhrajyoti Datta --- v6: Fix a yaml warning v7: Add vendor prefix speed-grade v8: Fix the warnings .../bindings/clock/xlnx,clocking-wizard.yaml | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 0000000..579bcc1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta + +description: + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +properties: + compatible: + const: xlnx,clocking-wizard + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + xlnx,speed-grade: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Speed grade of the device. + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - speed-grade + +additionalProperties: false + +examples: + - | + clock-generator@40040000 { + #clock-cells = <1>; + reg = <0x40040000 0x1000>; + compatible = "xlnx,clocking-wizard"; + xlnx,speed-grade = <1>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + clock-output-names = "clk_out1", "clk_out2", + "clk_out3", "clk_out4", "clk_out5", + "clk_out6", "clk_out7"; + }; +...