From patchwork Fri Jun 18 09:29:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 463248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72743C49361 for ; Fri, 18 Jun 2021 09:30:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 52814613E1 for ; Fri, 18 Jun 2021 09:30:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231889AbhFRJcw (ORCPT ); Fri, 18 Jun 2021 05:32:52 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:10138 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233277AbhFRJcW (ORCPT ); Fri, 18 Jun 2021 05:32:22 -0400 X-UUID: 4d4ce3623c5946a3b2d4d8a0b1bf9c16-20210618 X-UUID: 4d4ce3623c5946a3b2d4d8a0b1bf9c16-20210618 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 27514378; Fri, 18 Jun 2021 17:30:03 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Jun 2021 17:29:55 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Jun 2021 17:29:54 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Rob Herring , Felipe Balbi CC: Chunfeng Yun , Matthias Brugger , Thinh Nguyen , , , , , Subject: [PATCH v2 11/13] usb: mtu3: add helper to power on/down device Date: Fri, 18 Jun 2021 17:29:16 +0800 Message-ID: <1624008558-16949-12-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1624008558-16949-1-git-send-email-chunfeng.yun@mediatek.com> References: <1624008558-16949-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 972B8BE8ECA8DE72942E0558BB0F703C69AF39A3F1661AC3B5451BE01C2F0A332000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add helper to power on/down device ports and ip, it will be used when support device suspend/resume Signed-off-by: Chunfeng Yun --- v2: no changes --- drivers/usb/mtu3/mtu3_core.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c index 6d23acb4fffc..648e970d77ba 100644 --- a/drivers/usb/mtu3/mtu3_core.c +++ b/drivers/usb/mtu3/mtu3_core.c @@ -141,6 +141,28 @@ static void mtu3_device_disable(struct mtu3 *mtu) mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); } +static void mtu3_dev_power_on(struct mtu3 *mtu) +{ + void __iomem *ibase = mtu->ippc_base; + + mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); + if (mtu->is_u3_ip) + mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN); + + mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN); +} + +static void mtu3_dev_power_down(struct mtu3 *mtu) +{ + void __iomem *ibase = mtu->ippc_base; + + if (mtu->is_u3_ip) + mtu3_setbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN); + + mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN); + mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); +} + /* reset U3D's device module. */ static void mtu3_device_reset(struct mtu3 *mtu) { @@ -333,12 +355,7 @@ void mtu3_start(struct mtu3 *mtu) dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__, mtu3_readl(mbase, U3D_DEVICE_CONTROL)); - mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); - if (mtu->is_u3_ip) - mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN); - - mtu3_clrbits(mtu->ippc_base, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN); - + mtu3_dev_power_on(mtu); mtu3_csr_init(mtu); mtu3_set_speed(mtu, mtu->speed); @@ -360,12 +377,7 @@ void mtu3_stop(struct mtu3 *mtu) mtu3_dev_on_off(mtu, 0); mtu->is_active = 0; - - if (mtu->is_u3_ip) - mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN); - - mtu3_setbits(mtu->ippc_base, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN); - mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); + mtu3_dev_power_down(mtu); } /* for non-ep0 */