@@ -57,6 +57,27 @@
/* u2_phy_pll register */
#define CTRL_U2_FORCE_PLL_STB BIT(28)
+/* xHCI CSR */
+#define LS_EOF_CFG 0x930
+#define LSEOF_OFFSET 0x89
+
+#define FS_EOF_CFG 0x934
+#define FSEOF_OFFSET 0x2e
+
+#define SS_GEN1_EOF_CFG 0x93c
+#define SSG1EOF_OFFSET 0x78
+
+#define HFCNTR_CFG 0x944
+#define ITP_DELTA_CLK (0xa << 1)
+#define ITP_DELTA_CLK_MASK GENMASK(5, 1)
+#define FRMCNT_LEV1_RANG (0x12b << 8)
+#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
+
+#define SS_GEN2_EOF_CFG 0x990
+#define SSG2EOF_OFFSET 0x3c
+
+#define XSEOF_OFFSET_MASK GENMASK(11, 0)
+
/* usb remote wakeup registers in syscon */
/* mt8173 etc */
@@ -87,6 +108,46 @@ enum ssusb_uwk_vers {
SSUSB_UWK_V1_2, /* specific revision 1.2 */
};
+/*
+ * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
+ * is calculated from the frame counter clock 24M, but in fact, the clock
+ * is 48M, add workaround for it.
+ */
+static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
+{
+ struct device *dev = mtk->dev;
+ struct usb_hcd *hcd = mtk->hcd;
+ u32 value;
+
+ if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
+ return;
+
+ value = readl(hcd->regs + HFCNTR_CFG);
+ value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
+ value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
+ writel(value, hcd->regs + HFCNTR_CFG);
+
+ value = readl(hcd->regs + LS_EOF_CFG);
+ value &= ~XSEOF_OFFSET_MASK;
+ value |= LSEOF_OFFSET;
+ writel(value, hcd->regs + LS_EOF_CFG);
+
+ value = readl(hcd->regs + FS_EOF_CFG);
+ value &= ~XSEOF_OFFSET_MASK;
+ value |= FSEOF_OFFSET;
+ writel(value, hcd->regs + FS_EOF_CFG);
+
+ value = readl(hcd->regs + SS_GEN1_EOF_CFG);
+ value &= ~XSEOF_OFFSET_MASK;
+ value |= SSG1EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN1_EOF_CFG);
+
+ value = readl(hcd->regs + SS_GEN2_EOF_CFG);
+ value &= ~XSEOF_OFFSET_MASK;
+ value |= SSG2EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN2_EOF_CFG);
+}
+
static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
{
struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
@@ -368,6 +429,9 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
ret = xhci_mtk_ssusb_config(mtk);
if (ret)
return ret;
+
+ /* workaround only for mt8195 */
+ xhci_mtk_set_frame_interval(mtk);
}
ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
@@ -716,6 +780,7 @@ static const struct dev_pm_ops xhci_mtk_pm_ops = {
static const struct of_device_id mtk_xhci_of_match[] = {
{ .compatible = "mediatek,mt8173-xhci"},
+ { .compatible = "mediatek,mt8195-xhci"},
{ .compatible = "mediatek,mtk-xhci"},
{ },
};
There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz for those controllers. Note: the first controller no need set it. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- drivers/usb/host/xhci-mtk.c | 65 +++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+)