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Mon, 28 Aug 2023 07:59:25 -0700 Received: from xhdsgoud40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 28 Aug 2023 09:59:20 -0500 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc' Date: Mon, 28 Aug 2023 20:28:43 +0530 Message-ID: <1693234725-3615719-2-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1693234725-3615719-1-git-send-email-srinivas.goud@amd.com> References: <1693234725-3615719-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|SN7PR12MB7836:EE_ X-MS-Office365-Filtering-Correlation-Id: 97274339-79f2-4f0c-7ac3-08dba7d769e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m3d8k262wmPZtG/KERrPKi2QbR3m2X9QCHnVfV0TesQKHqSUgI9OfvzF4QWdhHrGqa8vBzP+8qsl6kKeW9sh8Qy6+imhq1fS6nj+ODSPsg/S54NTeCSAQtcArHqVKC17dwToDuxk8frR2LjUiZD+GfUM3y/WDkSmbOpcj2bpmOMrg0Vn3AqE7bobScGsC7k9YQL3IG07dLFKzEa9ntX5VzDLM6a/k24cW5n5G07i+ckSVM3qK6XTLJxi/fZoPM3jjJpVnao4z6QFwlCaGcI0HR7aaGaGXU9zF2ArZT8v1gVLyRRTMI8/lkWtsR5aYdipKywgyZnrpgIPdmRGnFQsB1LT2IKyqrqqr9wZxeBRAFQJqa+dJ+2bUlt5lF+3k5aGCZJ2tXcI1tQJDKanwFuyx5P/Bfslc6E0m8mXYqjxte8zQgmO0D0/MQrTuHpoD9ze1nzZAMfKj32IyOUflZ+pi+kM9HeC6HJrpYvIgSCPutTD4Da6D+89j7Qco5nPAOoOtjhpEjFS/2ha/rfWhAmZ/xPkXT5FxdHDIfDkXaP6Yzxm796mYlv8wT733J+La2Z+AVx7LIgM0OSacgmHo7QXTV9caiBu8wEHzf/5/X0W6TGSMwr8C9+vwmH612YPhZNTQ6JgHsb6hjk7we1hoAruR1MvYwqjAP6G2BqSgxX3CGHnHDw5/bUfMk6jK1AFtzTnWC2RzspfIJnQT07d1N+MX8eJVhaGejOG1eqLWbrRukmbXSlsBYcq3JVFja8wUzUyjK/xIGlCJJNQyXCFEnGVg3O1ZVg+z7AA7dJFB+858+o= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors. xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud --- Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..c842610 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN Tx and Rx fifo ECC enable flag (AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = ; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc }; - |