| Message ID | 1d555fbbac820e9b580da3e8c0db30e7d003c4b6.1651839494.git.lorenzo@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | [net-next,01/14] arm64: dts: mediatek: mt7986: introduce ethernet nodes | expand |
> +ð { > + status = "okay"; > + > + gmac0: mac@0 { > + compatible = "mediatek,eth-mac"; > + reg = <0>; > + phy-mode = "2500base-x"; > + > + fixed-link { > + speed = <2500>; > + full-duplex; > + pause; > + }; > + }; > + > + gmac1: mac@1 { > + compatible = "mediatek,eth-mac"; > + reg = <1>; > + phy-mode = "2500base-x"; > + > + fixed-link { > + speed = <2500>; > + full-duplex; > + pause; > + }; > + }; Are both connected to the switch? It just seems unusual two have two fixed-link ports. Andrew
> > +ð { > > + status = "okay"; > > + > > + gmac0: mac@0 { > > + compatible = "mediatek,eth-mac"; > > + reg = <0>; > > + phy-mode = "2500base-x"; > > + > > + fixed-link { > > + speed = <2500>; > > + full-duplex; > > + pause; > > + }; > > + }; > > + > > + gmac1: mac@1 { > > + compatible = "mediatek,eth-mac"; > > + reg = <1>; > > + phy-mode = "2500base-x"; > > + > > + fixed-link { > > + speed = <2500>; > > + full-duplex; > > + pause; > > + }; > > + }; > > Are both connected to the switch? It just seems unusual two have two > fixed-link ports. afaik mac design supports autoneg only in 10M/100M/1G mode and mt7986 gmac1 is connected to a 2.5Gbps phy on mt7986-ref board. Regards, Lorenzo > > Andrew
On Mon, May 09, 2022 at 06:35:42PM +0200, Lorenzo Bianconi wrote: > > > +ð { > > > + status = "okay"; > > > + > > > + gmac0: mac@0 { > > > + compatible = "mediatek,eth-mac"; > > > + reg = <0>; > > > + phy-mode = "2500base-x"; > > > + > > > + fixed-link { > > > + speed = <2500>; > > > + full-duplex; > > > + pause; > > > + }; > > > + }; > > > + > > > + gmac1: mac@1 { > > > + compatible = "mediatek,eth-mac"; > > > + reg = <1>; > > > + phy-mode = "2500base-x"; > > > + > > > + fixed-link { > > > + speed = <2500>; > > > + full-duplex; > > > + pause; > > > + }; > > > + }; > > > > Are both connected to the switch? It just seems unusual two have two > > fixed-link ports. > > afaik mac design supports autoneg only in 10M/100M/1G mode and mt7986 gmac1 > is connected to a 2.5Gbps phy on mt7986-ref board. The MAC does not normally perform autoneg, the PHY does. phylib/phylink then tells the MAC the result of the negotiation. If there is a SERDES/PCS involved, and it is performing the autoneg, phylink should get told about the result of the autoneg and it will tell the MAC the result. So the gmac1 should just have phy-handle pointing to the PHY, not a fixed link. Andrew
> On Mon, May 09, 2022 at 06:35:42PM +0200, Lorenzo Bianconi wrote: > > > > +ð { > > > > + status = "okay"; > > > > + > > > > + gmac0: mac@0 { > > > > + compatible = "mediatek,eth-mac"; > > > > + reg = <0>; > > > > + phy-mode = "2500base-x"; > > > > + > > > > + fixed-link { > > > > + speed = <2500>; > > > > + full-duplex; > > > > + pause; > > > > + }; > > > > + }; > > > > + > > > > + gmac1: mac@1 { > > > > + compatible = "mediatek,eth-mac"; > > > > + reg = <1>; > > > > + phy-mode = "2500base-x"; > > > > + > > > > + fixed-link { > > > > + speed = <2500>; > > > > + full-duplex; > > > > + pause; > > > > + }; > > > > + }; > > > > > > Are both connected to the switch? It just seems unusual two have two > > > fixed-link ports. > > > > afaik mac design supports autoneg only in 10M/100M/1G mode and mt7986 gmac1 > > is connected to a 2.5Gbps phy on mt7986-ref board. > > The MAC does not normally perform autoneg, the PHY > does. phylib/phylink then tells the MAC the result of the > negotiation. If there is a SERDES/PCS involved, and it is performing > the autoneg, phylink should get told about the result of the autoneg > and it will tell the MAC the result. > > So the gmac1 should just have phy-handle pointing to the PHY, not a > fixed link. > > Andrew adding Landen to the discussion to provide more hw details. @Landen: any inputs on it? Regards, Lorenzo
On Sat, 2022-05-14 at 17:49 +0800, Lorenzo Bianconi wrote: > > On Mon, May 09, 2022 at 06:35:42PM +0200, Lorenzo Bianconi wrote: > > > > > +ð { > > > > > + status = "okay"; > > > > > + > > > > > + gmac0: mac@0 { > > > > > + compatible = "mediatek,eth-mac"; > > > > > + reg = <0>; > > > > > + phy-mode = "2500base-x"; > > > > > + > > > > > + fixed-link { > > > > > + speed = <2500>; > > > > > + full-duplex; > > > > > + pause; > > > > > + }; > > > > > + }; > > > > > + > > > > > + gmac1: mac@1 { > > > > > + compatible = "mediatek,eth-mac"; > > > > > + reg = <1>; > > > > > + phy-mode = "2500base-x"; > > > > > + > > > > > + fixed-link { > > > > > + speed = <2500>; > > > > > + full-duplex; > > > > > + pause; > > > > > + }; > > > > > + }; > > > > > > > > Are both connected to the switch? It just seems unusual two > > > > have two > > > > fixed-link ports. > > > > > > afaik mac design supports autoneg only in 10M/100M/1G mode and > > > mt7986 gmac1 > > > is connected to a 2.5Gbps phy on mt7986-ref board. > > > > The MAC does not normally perform autoneg, the PHY > > does. phylib/phylink then tells the MAC the result of the > > negotiation. If there is a SERDES/PCS involved, and it is > > performing > > the autoneg, phylink should get told about the result of the > > autoneg > > and it will tell the MAC the result. > > > > So the gmac1 should just have phy-handle pointing to the PHY, not a > > fixed link. > > > > Andrew > > adding Landen to the discussion to provide more hw details. > @Landen: any inputs on it? The 2.5Gbps phy on mt7986-ref board enables the HW "rate adaption" function which phy fixes 2.5Gbps to MAC as well. If the link rate of Ethernet phy side is less than 2.5G, the 2.5Gbps phy HW will send pause frame to MAC to adapt the real Tx rate. By the way, the 2.5Gbps phy advertise all rates to link partner in HW default setting. Regards, Landen > > Regards, > Lorenzo
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 21e420829572..c5a4e999234c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -25,6 +25,101 @@ memory@40000000 { }; }; +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + phy5: phy@5 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + reset-gpios = <&pio 6 1>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + phy-mode = "2500base-x"; + }; + + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 694acf8f5b70..d2636a0ed152 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -222,6 +222,45 @@ ethsys: syscon@15000000 { #reset-cells = <1>; }; + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGMII0_TX250M_EN>, + <&sgmiisys0 CLK_SGMII0_RX250M_EN>, + <&sgmiisys0 CLK_SGMII0_CDR_REF>, + <&sgmiisys0 CLK_SGMII0_CDR_FB>, + <&sgmiisys1 CLK_SGMII1_TX250M_EN>, + <&sgmiisys1 CLK_SGMII1_RX250M_EN>, + <&sgmiisys1 CLK_SGMII1_CDR_REF>, + <&sgmiisys1 CLK_SGMII1_CDR_FB>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index d73467ea3641..5ed275dcd3dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -28,3 +28,94 @@ memory@40000000 { &uart0 { status = "okay"; }; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy5: phy@5 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <5>; + reset-gpios = <&pio 6 1>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-id67c9.de0a"; + reg = <6>; + phy-mode = "2500base-x"; + }; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +};