From patchwork Tue May 12 03:05:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 48324 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f197.google.com (mail-lb0-f197.google.com [209.85.217.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id AB8A62121F for ; Tue, 12 May 2015 03:06:16 +0000 (UTC) Received: by lbos2 with SMTP id s2sf42944639lbo.2 for ; Mon, 11 May 2015 20:06:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:date:from:to:cc:subject:message-id :references:mime-version:content-type:content-disposition :in-reply-to:user-agent:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=HO7xc3PY1tAy4Kr+GL1kAoQgpHaAcBFvoX3XGwSCgyI=; b=D0SkLP5SKbuFvqPNVU8cSsKwaj1F/h2tquunlmSqcVQ4r7xJhnQ0YWM2iAxdVodZNr KY3oYgRB2EILt3LEsM+61HmYtBtwNS0/5vMnVammjsPn8lENhKi6QJbj2ntaTVnodETK EKraxat2FXiYlXMfGcojOq1kBxUXLiA7rIAZscpCfQT0GzY1lTHDUNADVgsvrXXrj7os LaR+Iy+ABU/hWDtrClShrup974oI/kvjxKWSAQc/LNAfHfpfw8Fm8qVeUDzxkz4GJkbf vvsp5pYsfhylnEphs+DQ6FqNRKVfZfmvGt+TuAQBUGmW8PKQtJ3QQnmkSglJ2Mxrvl5o oiwg== X-Gm-Message-State: ALoCoQlId5KmPc+CNawq9OlajC8NE/OJeraC3Fm3UnQszsf8DibWtb/m7hAeASdQk/rJZWsbxVgk X-Received: by 10.112.26.5 with SMTP id h5mr9278313lbg.4.1431399975119; Mon, 11 May 2015 20:06:15 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.121.98 with SMTP id lj2ls678174lab.94.gmail; Mon, 11 May 2015 20:06:14 -0700 (PDT) X-Received: by 10.112.210.103 with SMTP id mt7mr8849204lbc.27.1431399974933; Mon, 11 May 2015 20:06:14 -0700 (PDT) Received: from mail-lb0-f175.google.com (mail-lb0-f175.google.com. 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[209.132.180.67]) by mx.google.com with ESMTP id z5si18869871pdk.254.2015.05.11.20.06.11; Mon, 11 May 2015 20:06:12 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752407AbbELDGD (ORCPT + 28 others); Mon, 11 May 2015 23:06:03 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:33322 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752191AbbELDF6 (ORCPT ); Mon, 11 May 2015 23:05:58 -0400 Received: by pdbnk13 with SMTP id nk13so164277157pdb.0 for ; Mon, 11 May 2015 20:05:57 -0700 (PDT) X-Received: by 10.67.10.105 with SMTP id dz9mr24019138pad.12.1431399957836; Mon, 11 May 2015 20:05:57 -0700 (PDT) Received: from leoy-linaro ([180.150.148.224]) by mx.google.com with ESMTPSA id pp6sm14443517pbb.17.2015.05.11.20.05.46 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 11 May 2015 20:05:57 -0700 (PDT) Date: Tue, 12 May 2015 11:05:42 +0800 From: Leo Yan To: Kevin Hilman Cc: Brent Wang , Mark Rutland , "dan.zhao@hisilicon.com" , "btw@mail.itp.ac.cn" , Catalin Marinas , "wangbinghui@hisilicon.com" , Will Deacon , "huxinwei@huawei.com" , Haojian Zhuang , Haifeng Yan , Rob Herring , Mike Turquette , Arnd Bergmann , "victor.lixin@hisilicon.com" , Xu Wei , Jaehoon Chung , "sledge.yanwei@huawei.com" , XinWei Kong , "heyunlei@huawei.com" , "puck.chen@hisilicon.com" , Zhangfei Gao , "z.liuxinliang@huawei.com" , "devicetree@vger.kernel.org" , Bintian Wang , Pawel Moll , Ian Campbell , Marc Zyngier , Tyler Baker , Olof Johansson , Rob Herring , Russell King - ARM Linux , "zhenwei.wang@hisilicon.com" , "w.f@huawei.com" , linux-arm-kernel , pebolle@tiscali.nl, Guodong Xu , Tomeu Vizoso , Stephen Boyd , "linux-kernel@vger.kernel.org" , Kumar Gala , "xuejiancheng@huawei.com" , Jorge Ramirez-Ortiz , "xuyiping@hisilicon.com" , "Liguozhu (Kenneth)" Subject: Re: [PATCH v5 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC Message-ID: <20150512030542.GA5889@leoy-linaro> References: <1431007225-8513-1-git-send-email-bintian.wang@huawei.com> <7ha8xgi10e.fsf@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: leo.yan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , hi Kevin, On Mon, May 11, 2015 at 05:20:54PM -0700, Kevin Hilman wrote: > On Thu, May 7, 2015 at 4:11 PM, Brent Wang wrote: > > Hello Kevin, > > > > 2015-05-08 4:30 GMT+08:00 Kevin Hilman : > >> Bintian Wang writes: > >> > >>> Hi6220 is one mobile solution of Hisilicon, this patchset contains > >>> initial support for Hi6220 SoC and HiKey development board, which > >>> supports octal ARM Cortex A53 cores. Initial support is minimal and > >>> includes just the arch configuration, clock driver, device tree > >>> configuration. > >>> > >>> PSCI is enabled in device tree and there is no problem to boot all the > >>> octal cores, and the CPU hotplug is also working now, you can download > >>> and compile the latest firmware based on the following link to run this > >>> patch set: > >>> https://github.com/96boards/documentation/wiki/UEFI > >> > >> Do you have any tips for booting this using the HiSi bootloader? It > >> seems that I need to add the magic hisi,boardid property for dtbTool to > >> work. Could you share what that magic value is? > > Yes, you need it. > > Hisilicon has many different development boards and those boards have some > > different hardware configuration, so we need different device tree > > files for them. > > the original hisi,boardid is used to distinguish different boards and > > used by the > > bootloader to judge which device tree to use at boot-up. > > > >> and maybe add it to the wiki someplace? > > Maybe add to section "Known Issues" in > > "https://github.com/96boards/documentation/wiki/UEFI" > > is a good choice, I will update this section later. > > You updated the wiki, but you didn't specify what the value should be > for this to work with the old bootloader. > > Can you please give the value of that property? > > Also, have you tested this series with the old bootloader as well? Below are my testing result w/t Bintian's patches and Hisilicon old bootloader: - Need add property "hisi,boardid" into dts; - Need change cpu enable-method from "psci" to "spin-table"; - The bootloader has not initialized register *cntfrq_el0* so will introduce the failure during init arch timer. For init cntfrq_el0, we need fix this issue in Hisilicon's old bootloader, rather than directly add "clock-frequency" for arch timer's node in DTS. i will try to commit one patch for fix this issue for Hisilicon's old bootloader. So i think upper issues mainly are introduced by Hisilicon's old bootloader but not come from Bintian's patches. How about u think for this? Below is my local diff which is used to compatible w/t Hisilicon's old bootloader; Just for your reference. Thanks, Leo Yan ---8<--- --- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index e36a539..fd1f89e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -14,6 +14,7 @@ / { model = "HiKey Development Board"; + hisi,boardid = <0 0 4 3>; compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; aliases { diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 229937f..8ade3d9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -13,11 +13,6 @@ #address-cells = <2>; #size-cells = <2>; - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -57,56 +52,64 @@ compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x0>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x1>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x2>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x3>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; cpu4: cpu@100 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x100>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; cpu5: cpu@101 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x101>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; cpu6: cpu@102 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x102>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; cpu7: cpu@103 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x103>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x740fff8>; }; }; @@ -129,6 +132,7 @@ , , ; + clock-frequency = <1200000>; }; soc {