From patchwork Mon Jan 9 19:43:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 90566 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp246020qgi; Mon, 9 Jan 2017 11:44:58 -0800 (PST) X-Received: by 10.99.251.69 with SMTP id w5mr166522576pgj.124.1483991098018; Mon, 09 Jan 2017 11:44:58 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e5si89613614pgg.98.2017.01.09.11.44.57; Mon, 09 Jan 2017 11:44:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763703AbdAIToz (ORCPT + 7 others); Mon, 9 Jan 2017 14:44:55 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:23322 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763688AbdAITos (ORCPT ); Mon, 9 Jan 2017 14:44:48 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v09Ji12D006661; Mon, 9 Jan 2017 13:44:01 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v09Ji03s010668; Mon, 9 Jan 2017 13:44:01 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 9 Jan 2017 13:44:00 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v09Ji0cG014834; Mon, 9 Jan 2017 13:44:00 -0600 Received: from localhost (irmo.am.dhcp.ti.com [128.247.83.68]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v09Ji0307919; Mon, 9 Jan 2017 13:44:00 -0600 (CST) From: Suman Anna To: Santosh Shilimkar CC: Philipp Zabel , Rob Herring , Russell King , , , , Andrew Davis , Suman Anna Subject: [PATCH 5/5] ARM: dts: keystone-k2e: Add PSC reset controller node Date: Mon, 9 Jan 2017 13:43:58 -0600 Message-ID: <20170109194358.27271-6-s-anna@ti.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170109194358.27271-1-s-anna@ti.com> References: <20170109194358.27271-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Power Sleep Controller (PSC) module contains specific memory-mapped registers that can be used to perform reset management using specific bits for the DSPs available on the SoC. The PSC is defined using a syscon node, and the reset functionality is defined using a child syscon reset controller node. Add this syscon reset controller node as well as the reset control data for the resets it supports for the 66AK2E SoCs. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna --- arch/arm/boot/dts/keystone-k2e.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 9d1d8a64d10e..c5983418c42c 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include + / { compatible = "ti,k2e", "ti,keystone"; model = "Texas Instruments Keystone 2 Edison SoC"; @@ -94,6 +96,17 @@ }; }; + psc: power-sleep-controller@02350000 { + pscrst: psc-reset-controller { + compatible = "ti,k2e-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + >; + }; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller;