From patchwork Fri Sep 22 11:47:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 114018 Delivered-To: patch@linaro.org Received: by 10.80.163.150 with SMTP id s22csp2986073edb; Fri, 22 Sep 2017 04:47:24 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAly/PyY2YNffqDfPyVgsCcT+8zpkaEMkYGi8WhWSRz1ry7qi62rdDY56ssu/38r7356NhF X-Received: by 10.84.229.7 with SMTP id b7mr8584229plk.75.1506080844416; Fri, 22 Sep 2017 04:47:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506080844; cv=none; d=google.com; s=arc-20160816; b=jukdhhdLBN2VpSL3lp3YX3ewd80inHR8XuFdOyR1+/GSzSSwtJ+g5Qgyqe/+2dE0ev WEWhTph7QKKfndiGvsbEawmFpB9s9bZdIpoqyYAiziEozGamYoHN4zbdVMQTXrlbjsHO QDTh4IYiTUo0S1zVObY/1rHs0QleYam/gCjOvoVoYJDEhmv7SrhJUQY7EMnBfDEW+HjZ Jjpigpy8L0pINMZtggGg5Vz8+Sl3IULAxwUp0k0Z4asCku5s9j1+sD1yaJMHvw0HjjdI raLzR94qCsoMfLatxhTKVYm1oyZeGs3Ce/kGy1f19B4VIAOF0TD+W+65gu/yTKqMDqcK vdwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=5Bnh81LakobApMPvvzZi6sqRCBfaKcNQNvk3oFoYUUY=; b=q7oglnQARMI5z8TbDi2cKnsiiJogCEE3d7c5W9tMx5+Qj1suqLSMQIdY6/YSkPuulb WCtW7H6poQyUqaMtJqT7NrY84OTeTwYFL5KwsN3tb2pPrU134Lt0yHT3kbQsgg2JUljB rVqw75PaUzVJpRb1LPtF/rfeT+HE2EHB5MPPr+9cx3Hujow43Ab/PUKy71W4TN7X1E6y IfecDyjT6ins5I15M6ybs1B7KQq69naXvE/zv1dcPjpoOevHwTOpHHJbjxypz0qqo8Us snW4qWAUVJkvWs3eChi4tGLcqZz0+XrRWR/AN5Qtchnfd76C2LdcXimpqtFa+5aprerC WKCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t5si2717634pgo.671.2017.09.22.04.47.24; Fri, 22 Sep 2017 04:47:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752317AbdIVLrX (ORCPT + 6 others); Fri, 22 Sep 2017 07:47:23 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:59895 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752313AbdIVLrW (ORCPT ); Fri, 22 Sep 2017 07:47:22 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 53B8F209B1; Fri, 22 Sep 2017 13:47:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id C8238208D1; Fri, 22 Sep 2017 13:47:05 +0200 (CEST) From: Maxime Ripard To: Mauro Carvalho Chehab , Mark Rutland , Rob Herring Cc: Laurent Pinchart , linux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka , Richard Sproul , Alan Douglas , Steve Creaney , Thomas Petazzoni , Boris Brezillon , =?utf-8?q?Niklas_S=C3=B6derlund?= , Hans Verkuil , Sakari Ailus , Benoit Parrot , nm@ti.com, Maxime Ripard Subject: [PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device Tree bindings Date: Fri, 22 Sep 2017 13:47:02 +0200 Message-Id: <20170922114703.30511-2-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170922114703.30511-1-maxime.ripard@free-electrons.com> References: <20170922114703.30511-1-maxime.ripard@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Cadence MIPI-CSI2 RX controller is a CSI2 bridge that supports up to 4 video streams and can output on up to 4 CSI-2 lanes, depending on the hardware implementation. It can operate with an external D-PHY, an internal one or no D-PHY at all in some configurations. Signed-off-by: Maxime Ripard --- .../devicetree/bindings/media/cdns,csi2tx.txt | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2tx.txt -- 2.13.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt new file mode 100644 index 000000000000..5fb70bba910e --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt @@ -0,0 +1,97 @@ +Cadence MIPI-CSI2 TX controller +=============================== + +The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to +4 CSI lanes in output, and up to 4 different pixel streams in input. + +Required properties: + - compatible: must be set to "cdns,csi2tx" + - reg: base address and size of the memory mapped region + - clocks: phandles to the clocks driving the controller + - clock-names: must contain: + * esc_clk: escape mode clock + * p_clk: register bank clock + * pixel_if[0-3]_clk: pixel stream output clock, one for each stream + implemented in hardware, between 0 and 3 + +Optional properties + - phys: phandle to the D-PHY. If it is set, phy-names need to be set + - phy-names: must contain dphy + +Required subnodes: + - ports: A ports node with one port child node per device input and output + port, in accordance with the video interface bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + port nodes numbered as follows. + + Port Description + ----------------------------- + 0 CSI-2 output + 1 Stream 0 input + 2 Stream 1 input + 3 Stream 2 input + 4 Stream 3 input + + The stream input port nodes are optional if they are not + connected to anything at the hardware level or implemented + in the design. + +Example: + +csi2tx: csi-bridge@0d0e1000 { + compatible = "cdns,csi2tx"; + reg = <0x0d0e1000 0x1000>; + clocks = <&byteclock>, <&byteclock>, + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "p_clk", "esc_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2tx_out: endpoint { + remote-endpoint = <&remote_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2tx_in_stream0: endpoint { + remote-endpoint = <&stream0_out>; + }; + }; + + port@2 { + reg = <2>; + + csi2tx_in_stream1: endpoint { + remote-endpoint = <&stream1_out>; + }; + }; + + port@3 { + reg = <3>; + + csi2tx_in_stream2: endpoint { + remote-endpoint = <&stream2_out>; + }; + }; + + port@4 { + reg = <4>; + + csi2tx_in_stream3: endpoint { + remote-endpoint = <&stream3_out>; + }; + }; + }; +};