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[209.132.180.67]) by mx.google.com with ESMTP id a140-v6si4957614pfd.35.2018.07.27.11.48.23; Fri, 27 Jul 2018 11:48:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=K+GR4lGW; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389130AbeG0ULb (ORCPT + 5 others); Fri, 27 Jul 2018 16:11:31 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:38620 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389121AbeG0ULb (ORCPT ); Fri, 27 Jul 2018 16:11:31 -0400 Received: by mail-pg1-f195.google.com with SMTP id k3-v6so3723779pgq.5 for ; Fri, 27 Jul 2018 11:48:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QH1TTvPQlofOSOVaK9da0D5f9V4qdv+e+owka7pRNb0=; b=K+GR4lGWhCuXX4ELqS31FNL13z25WRQ7VS/eNMPYgXPTwhv1YkoyfpsLR9DpEvOo9o lhMLFVSEWikYTf4yOYldjoauk0MzTMumZFDjftJPCDxp49E6ZWmAp/ZpfiAYTPFhx5LT zlXnykV5kOGFIMQpWcBXlJnc5j/+p/ecBVavc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QH1TTvPQlofOSOVaK9da0D5f9V4qdv+e+owka7pRNb0=; b=dWQzZfbblDiPMv+B0E26H/DB33TGMGgN4A/kBAEF3qMotH+JHq3zVGEwurKpNTausM V2RCX09S5fjAQXomrEaOqoF2nhNwlFYv2XrtdvQkcz+cqKenZIWaiW1JlaaUp6TUs35K uXbaBotdouRl7n+8K6IffNtBqdFrTJke+lHcwNV+3+YyCaeWo82QYpdNg811U0Yp7c41 03keKW5o1RDzV9qFHul+4775KilmODAT/9Y768zFyfhVelNaWdm9KYsi4FgVuEyEWYgS 5W/wEOSH9cB9IcGzSPw9k4GGFBYhD2oBK4ApC0OCfp+LzZcis0ZWlF7FA4iw2PORNcCC yiwQ== X-Gm-Message-State: AOUpUlFIsPkrSJyJ87RFSkCRGsUzB6uWhacl42uDSMyrGzsEwx/KsvJV ZCkpYDm6ejOoeMod9AepU2wKfExziw== X-Received: by 2002:a63:d20e:: with SMTP id a14-v6mr7134377pgg.226.1532717301498; Fri, 27 Jul 2018 11:48:21 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7308:c330:41b:cc59:b463:ec7b]) by smtp.gmail.com with ESMTPSA id t69-v6sm13817959pfj.7.2018.07.27.11.48.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 11:48:21 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH 8/9] clk: actions: Add Actions Semi S700 SoC Reset Management Unit support Date: Sat, 28 Jul 2018 00:15:26 +0530 Message-Id: <20180727184527.13287-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180727184527.13287-1-manivannan.sadhasivam@linaro.org> References: <20180727184527.13287-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Reset Management Unit (RMU) support for Actions Semi S700 SoC. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/owl-s700.c | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c index e7cacd677275..d9c0c7870135 100644 --- a/drivers/clk/actions/owl-s700.c +++ b/drivers/clk/actions/owl-s700.c @@ -20,8 +20,10 @@ #include "owl-gate.h" #include "owl-mux.h" #include "owl-pll.h" +#include "owl-reset.h" #include +#include #define CMU_COREPLL (0x0000) #define CMU_DEVPLL (0x0004) @@ -569,20 +571,69 @@ static struct clk_hw_onecell_data s700_hw_clks = { .num = CLK_NR_CLKS, }; +static struct owl_reset_map s700_resets[] = { + [RESET_DE] = { CMU_DEVRST0, BIT(0) }, + [RESET_LCD0] = { CMU_DEVRST0, BIT(1) }, + [RESET_DSI] = { CMU_DEVRST0, BIT(2) }, + [RESET_CSI] = { CMU_DEVRST0, BIT(13) }, + [RESET_SI] = { CMU_DEVRST0, BIT(14) }, + [RESET_I2C0] = { CMU_DEVRST1, BIT(0) }, + [RESET_I2C1] = { CMU_DEVRST1, BIT(1) }, + [RESET_I2C2] = { CMU_DEVRST1, BIT(2) }, + [RESET_I2C3] = { CMU_DEVRST1, BIT(3) }, + [RESET_SPI0] = { CMU_DEVRST1, BIT(4) }, + [RESET_SPI1] = { CMU_DEVRST1, BIT(5) }, + [RESET_SPI2] = { CMU_DEVRST1, BIT(6) }, + [RESET_SPI3] = { CMU_DEVRST1, BIT(7) }, + [RESET_UART0] = { CMU_DEVRST1, BIT(8) }, + [RESET_UART1] = { CMU_DEVRST1, BIT(9) }, + [RESET_UART2] = { CMU_DEVRST1, BIT(10) }, + [RESET_UART3] = { CMU_DEVRST1, BIT(11) }, + [RESET_UART4] = { CMU_DEVRST1, BIT(12) }, + [RESET_UART5] = { CMU_DEVRST1, BIT(13) }, + [RESET_UART6] = { CMU_DEVRST1, BIT(14) }, + [RESET_KEY] = { CMU_DEVRST1, BIT(24) }, + [RESET_GPIO] = { CMU_DEVRST1, BIT(25) }, + [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) }, +}; + static struct owl_clk_desc s700_clk_desc = { .clks = s700_clks, .num_clks = ARRAY_SIZE(s700_clks), .hw_clks = &s700_hw_clks, + + .resets = s700_resets, + .num_resets = ARRAY_SIZE(s700_resets), }; static int s700_clk_probe(struct platform_device *pdev) { struct owl_clk_desc *desc; + struct owl_reset *reset; + int ret; desc = &s700_clk_desc; owl_clk_regmap_init(pdev, desc); + /* + * FIXME: Reset controller registration should be moved to + * common code, once all SoCs of Owl family supports it. + */ + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.ops = &owl_reset_ops; + reset->rcdev.nr_resets = desc->num_resets; + reset->reset_map = desc->resets; + reset->regmap = desc->regmap; + + ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev); + if (ret) + dev_err(&pdev->dev, "Failed to register reset controller\n"); + return owl_clk_probe(&pdev->dev, desc->hw_clks); }