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[209.132.180.67]) by mx.google.com with ESMTP id 31-v6si9583201pla.129.2018.08.10.02.53.38; Fri, 10 Aug 2018 02:53:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ry8W+mNi; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728011AbeHJMWq (ORCPT + 5 others); Fri, 10 Aug 2018 08:22:46 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:33318 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727486AbeHJMWp (ORCPT ); Fri, 10 Aug 2018 08:22:45 -0400 Received: by mail-pl0-f65.google.com with SMTP id b90-v6so3851480plb.0 for ; Fri, 10 Aug 2018 02:53:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aSAAa+s6BC6vmUVrsIHnMhod2TH+xc3yY1ux/OMaXVk=; b=Ry8W+mNiPbEr7ySiW6xp3QCzonGbNdhrFXMQc9y0rPup1Kykmlv1P3eBScv/3QPzhA x4AXJmUbLX7XDHFGC8IfQI/y9CZSP+/ooQ4yl9c7J3qLogdn/G+UVHJUb5JB2AWmr9Pt TLjd+DXU/aW9g6cUjolrqn4Ne2/jxbSuwaCTU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aSAAa+s6BC6vmUVrsIHnMhod2TH+xc3yY1ux/OMaXVk=; b=QACUL7+Z3/0fD+Z2DbEOuvtlxd9UO9ftTOks/l+7ba02729XwFDTV2sJPQ3qICw73I XwVEniK/0INSpVZFfEcxx3i0rrIGylHBo15LxlBQyRJ7Z8ZGVg6YGWVjNfebFOLrx3UG DH12PV/1bmKpLW4AV2nTF6ECgrg1nOO7YPO4xUNOg3YnxBcAxko2DjcQDZ3/28PlhMd1 Fc0Rf3GqnI924moY1J2LdpH4fZFk28BFPTx4xMBCPJhoRsLqb3GzbM6oJz8xWWiwaN6j ax06ldnNAbNyiuTzRJmiOMr0h2qzxR1jnNcS+Ax9S+6yLETiRDC9ZFybfhOSvI7UYRSV Nz6g== X-Gm-Message-State: AOUpUlG3EqCjGlKoSQRBx42prChxpo4Ok61p3WsuPFJPeG98wWkIWlte JuSx6u5E5eoVgs/NLcW3g9ki X-Received: by 2002:a17:902:a58b:: with SMTP id az11-v6mr5441735plb.36.1533894816716; Fri, 10 Aug 2018 02:53:36 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6391:e983:9562:f5f7:1a60:4363]) by smtp.gmail.com with ESMTPSA id n83-v6sm25315120pfk.19.2018.08.10.02.53.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 02:53:36 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH v3 7/9] clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support Date: Fri, 10 Aug 2018 15:21:11 +0530 Message-Id: <20180810095113.25292-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180810095113.25292-1-manivannan.sadhasivam@linaro.org> References: <20180810095113.25292-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Reset Management Unit (RMU) support for Actions Semi Owl SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Kconfig | 1 + drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-common.h | 2 + drivers/clk/actions/owl-reset.c | 66 ++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-reset.h | 31 +++++++++++++++ 5 files changed, 101 insertions(+) create mode 100644 drivers/clk/actions/owl-reset.c create mode 100644 drivers/clk/actions/owl-reset.h -- 2.17.1 diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig index dc38c85a4833..04f0a6355726 100644 --- a/drivers/clk/actions/Kconfig +++ b/drivers/clk/actions/Kconfig @@ -2,6 +2,7 @@ config CLK_ACTIONS bool "Clock driver for Actions Semi SoCs" depends on ARCH_ACTIONS || COMPILE_TEST select REGMAP_MMIO + select RESET_CONTROLLER default ARCH_ACTIONS if CLK_ACTIONS diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 78c17d56f991..ccfdf9781cef 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -7,6 +7,7 @@ clk-owl-y += owl-divider.o clk-owl-y += owl-factor.o clk-owl-y += owl-composite.o clk-owl-y += owl-pll.o +clk-owl-y += owl-reset.o # SoC support obj-$(CONFIG_CLK_OWL_S700) += owl-s700.o diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h index 56f01f7774aa..5a866a8b913d 100644 --- a/drivers/clk/actions/owl-common.h +++ b/drivers/clk/actions/owl-common.h @@ -26,6 +26,8 @@ struct owl_clk_desc { struct owl_clk_common **clks; unsigned long num_clks; struct clk_hw_onecell_data *hw_clks; + const struct owl_reset_map *resets; + unsigned long num_resets; struct regmap *regmap; }; diff --git a/drivers/clk/actions/owl-reset.c b/drivers/clk/actions/owl-reset.c new file mode 100644 index 000000000000..203f8f34a8d4 --- /dev/null +++ b/drivers/clk/actions/owl-reset.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// +// Actions Semi Owl SoCs Reset Management Unit driver +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include +#include + +#include "owl-reset.h" + +static int owl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->reset_map[id]; + + return regmap_update_bits(reset->regmap, map->reg, map->bit, 0); +} + +static int owl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->reset_map[id]; + + return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit); +} + +static int owl_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + owl_reset_assert(rcdev, id); + udelay(1); + owl_reset_deassert(rcdev, id); + + return 0; +} + +static int owl_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->reset_map[id]; + u32 reg; + int ret; + + ret = regmap_read(reset->regmap, map->reg, ®); + if (ret) + return ret; + + /* + * The reset control API expects 0 if reset is not asserted, + * which is the opposite of what our hardware uses. + */ + return !(map->bit & reg); +} + +const struct reset_control_ops owl_reset_ops = { + .assert = owl_reset_assert, + .deassert = owl_reset_deassert, + .reset = owl_reset_reset, + .status = owl_reset_status, +}; diff --git a/drivers/clk/actions/owl-reset.h b/drivers/clk/actions/owl-reset.h new file mode 100644 index 000000000000..10f5774979a6 --- /dev/null +++ b/drivers/clk/actions/owl-reset.h @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// +// Actions Semi Owl SoCs Reset Management Unit driver +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_RESET_H_ +#define _OWL_RESET_H_ + +#include + +struct owl_reset_map { + u32 reg; + u32 bit; +}; + +struct owl_reset { + struct reset_controller_dev rcdev; + const struct owl_reset_map *reset_map; + struct regmap *regmap; +}; + +static inline struct owl_reset *to_owl_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct owl_reset, rcdev); +} + +extern const struct reset_control_ops owl_reset_ops; + +#endif /* _OWL_RESET_H_ */