From patchwork Mon Sep 10 15:13:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 146341 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp2607978ljw; Mon, 10 Sep 2018 08:14:45 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdanq5NIvXtm3YoqG1qgd2Os+UfeZanoXp1gqM05AqnT+YNRvAvXLIvJCCt0j7/t9pymujyE X-Received: by 2002:a63:a35f:: with SMTP id v31-v6mr23318878pgn.261.1536592485102; Mon, 10 Sep 2018 08:14:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536592485; cv=none; d=google.com; s=arc-20160816; b=Ox0iMiTtWrKVZDVnmgYDKksZnNM8rzEZ6/82P+GWoyIH1wwc2+vfdeSH0MVEqiUhyC IlRVksz+jmJp0QAtcAZk14HYnCoOyR3bKxvjWH4xRxhHmqN9BGnwxwP42qpacyR6Ei/q B1ioBE6m5CTN+SLxTEjEZNBTOUPQpoX/h3ZaPzSYe0zXwWd+Hyjuv/w7/4OZbtCBX6Wo Bwi+vC9xHrnJxh1KzXfgWthWojmj13JcG1IpyFapjIlClJQyhp3Y71eSyCPdm3+fepyA w96ROhNEBzAI3R12Bq46ELAOPSPJi6GU8E18ieQhrTHD902kegCIv1CGBUmk+XlfE3kJ FdkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=znfZBHVDWIral+xe0reTBGcJ7dk9ivMDjn8uEGJfcT8=; b=07UxSATBXz8fWDr5w1vfnZ51BY+g/slrW8GVehIaSSZqTk1ZQlw0dmKPNjozPNwAm9 enpaw78iZmhDzQADbq0G3vRTUirwaRvbp8oJ2ojo73xXNyxSkpP1bxVtnt3Us5Icy0Yi ARyI/ho2eO6ZZaJ4HFmuiPRvUV5X3m7tPl6awjzYUDFaWT5lz6QKQiLU7Jf51kTwz3GQ l3D82yauht7EyLvpy1Lx0Ug5AfZw/5l+RJgiyZuIMIfcI5wkAVdVw+49IV++zp3b3F2s BtqkUwh8hTvauVFXFQm2Wrl8T5vsa9A7KZXWeC5GjmA1i8K1zVHc/dz0PVE2XrK0alyv HpJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Al3A4xuT; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n10-v6si18589258pgf.415.2018.09.10.08.14.44; Mon, 10 Sep 2018 08:14:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Al3A4xuT; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728467AbeIJUJR (ORCPT + 6 others); Mon, 10 Sep 2018 16:09:17 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:34122 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727815AbeIJUJR (ORCPT ); Mon, 10 Sep 2018 16:09:17 -0400 Received: by mail-pl1-f195.google.com with SMTP id f6-v6so9903787plo.1 for ; Mon, 10 Sep 2018 08:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=znfZBHVDWIral+xe0reTBGcJ7dk9ivMDjn8uEGJfcT8=; b=Al3A4xuT8zmMMUoHO2mMDnqXf7kGCK9hCVkQJSQZFZzcSy+jmsteTH3xgr6KchUnj1 2j1TY1/JwFbt7AnCtLEHEsqI81Ish0NmRq1zZTjIu9xkJ9SgOxdf5wBa3TGzYWZoukb+ CKfaB4Fv5Gj/U4qLXVxDT6wTw7vhRDNz1ZsRQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=znfZBHVDWIral+xe0reTBGcJ7dk9ivMDjn8uEGJfcT8=; b=t35uISGc/KQSwxmDEM8vq+Usmf7z4UAy6abIPgbtoIExF8edOdjuoE+ZEdyntr/bkI AM/ie/ab30gkIC4sY1dA0S8pLqhi3VRU15LaCKzgvkJkaWybMbyFxFJwj/IV/45CNd8k y7M2NdzPBfC7bhU9O0JViGr6QjuXzqNhbbFYb9c0nR5x8JUTz/ykJk9d6GVraXJKDp1C JROziFKnompNzC0L6ke083EqshMPQ5A5eTqJSY7raRVRM7iFamvHccW2/C0o41DB/QTe qycP4j6OrwvqPG4mDVDLVOIkZ8MwIeYX/44+KvWCxn7U1XRr1FYmE4Y7bOM2S08PAntg oGhw== X-Gm-Message-State: APzg51D+PB8K3ExB665SOA3l39wUZhBp0Gsvj3MhalsqKSxsBu/y/tZ6 c3tISICukhc8W6UMxDctSWLR X-Received: by 2002:a17:902:740a:: with SMTP id g10-v6mr22947347pll.22.1536592483495; Mon, 10 Sep 2018 08:14:43 -0700 (PDT) Received: from localhost.localdomain ([2405:204:728c:6bba:60a8:6c40:2817:7ee1]) by smtp.gmail.com with ESMTPSA id e202-v6sm26703907pfh.16.2018.09.10.08.14.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Sep 2018 08:14:42 -0700 (PDT) From: Manivannan Sadhasivam To: heiko@sntech.de, robh+dt@kernel.org Cc: vicencb@gmail.com, shawn.lin@rock-chips.com, ezequiel@collabora.com, enric.balletbo@collabora.com, pbrobinson@gmail.com, tom@vamrs.com, dev@vamrs.com, stephen@vamrs.com, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 3/4] arm64: boot: dts: rockchip: Add support for Rock960 board Date: Mon, 10 Sep 2018 20:43:55 +0530 Message-Id: <20180910151356.25946-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180910151356.25946-1-manivannan.sadhasivam@linaro.org> References: <20180910151356.25946-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree support for Rock960 board, one of the Consumer Edition boards of the 96Boards family. This board support utilizes the common Rock960 family board support that includes Ficus 96Board. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-rock960.dts | 139 ++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts -- 2.17.1 diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index b0092d95b574..57c0d76458e6 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts new file mode 100644 index 000000000000..281f3d79b38e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Linaro Ltd. + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" + +/ { + model = "96boards Rock960"; + compatible = "vamrs,rk3399-rock960", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +};