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[209.132.180.67]) by mx.google.com with ESMTP id e34-v6si28005705plb.2.2018.09.20.23.01.34; Thu, 20 Sep 2018 23:01:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bpaoA3kk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388826AbeIULst (ORCPT + 6 others); Fri, 21 Sep 2018 07:48:49 -0400 Received: from mail-it1-f193.google.com ([209.85.166.193]:35410 "EHLO mail-it1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389254AbeIULsh (ORCPT ); Fri, 21 Sep 2018 07:48:37 -0400 Received: by mail-it1-f193.google.com with SMTP id 139-v6so747692itf.0 for ; Thu, 20 Sep 2018 23:01:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gzU6v5xWc9dIvDgqXb1SE74zda+5lHaIqfgTIAAAstI=; b=bpaoA3kkHShq4oS3lHp2c7bmW0qp5xOo0UABMUEJnzsSAOGRf8UsHbWeOQNaIeaA6x ajPUia5/j2rJ8Tf/Q36VGIaKBkWDwv7Ud9mn5xEUAgnq4zTrhryvsVu4JhzTX1UN3Bn4 M+vgRt4xfR+ko28KrD/b3lXnRDKpYslIDQ/IE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gzU6v5xWc9dIvDgqXb1SE74zda+5lHaIqfgTIAAAstI=; b=EchbfbYGCLp5AkThDtRf7ddGpCKZiBfiuxRNHf4FrRjbp3BEtgr2IzwP0uMtbWIiHM 3AXP+K7gIFCnuyQ4/dLan4YHU37UmHMinJaLjjlpgm3q9jqMp7KHlBAkGMhJrSXHMwng qy9bdF/bhJ414MCv5w2R8qxO2J5l0aLTgYkPc0ZUqvqIpc+kbYwoyiGC1rXWqgAeG9oQ 9HXy69ufEay8kYLeQXlfdHIiHBk11LYWax2hcSkcDTqXncYxjoSWRdZrhgTcfOhvDMjz fXWaWfFQDD9x5PpLH2Vf30uwZ/iC/9LUcMaHCaDk2wZ516Kz+3deTnFRZXytRsgaQsk9 B1tA== X-Gm-Message-State: APzg51Cbrxg80+bkNFyn2GAq8jDtBf/v8G+SsqIEnspu1dKJVWyQU+rR 3Gt7zz2Dpq2p2sMGp4fTEuzW X-Received: by 2002:a24:1ad2:: with SMTP id 201-v6mr4968137iti.18.1537509679527; Thu, 20 Sep 2018 23:01:19 -0700 (PDT) Received: from localhost.localdomain ([209.82.80.116]) by smtp.gmail.com with ESMTPSA id b195-v6sm1973875itc.42.2018.09.20.23.01.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Sep 2018 23:01:19 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kucheria@linaro.org, linux-clk@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 3/4] arm64: dts: hisilicon: Source SoC clock for UART6 Date: Thu, 20 Sep 2018 23:01:02 -0700 Message-Id: <20180921060103.21370-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921060103.21370-1-manivannan.sadhasivam@linaro.org> References: <20180921060103.21370-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove fixed clock and source SoC clock for UART6 for HiSilicon Hi3670 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 8a0ee4b08886..34a2f0dbc6f7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -187,17 +187,12 @@ #clock-cells = <1>; }; - uart6_clk: clk_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - uart6: serial@fff32000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfff32000 0x0 0x1000>; interrupts = ; - clocks = <&uart6_clk &uart6_clk>; + clocks = <&crg_ctrl HI3670_CLK_UART6>, + <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; };