From patchwork Mon Dec 3 21:31:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 152778 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7320423ljp; Mon, 3 Dec 2018 13:35:27 -0800 (PST) X-Google-Smtp-Source: AFSGD/WQfvZ5xFaAI513lI0gt0U8/MlnOZpT6vAtBI4meO3I0RS49ooUszZyGrrBsU0gFL+bXi+G X-Received: by 2002:a17:902:161:: with SMTP id 88mr17977992plb.306.1543872927585; Mon, 03 Dec 2018 13:35:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543872927; cv=none; d=google.com; s=arc-20160816; b=aIoDOH/OUhIix2UqTqugva6TMjlcNeOmdCnUCIUJ7v4GXPAKMRA6AhFSdUwoK3I9Jf IoUN5bBy7dhtACex8IRwNY4upbodEA8SwfXaMh0fYJGpTlVM57y2NZV3I8+2nRmjaGsa ezrYr7VP6NWIMgLLxuZPZ4M6tN9U4yiKITKczF2VP5DiWcObWfi50CmM/f38fPHhe2XH 97Nxbj3/vVSfjMER4rv7PgQIkQlQvKHAnYbcyfZbfQS+xtb33Kt6V0EcoCzBC2VKeFcr nHisCbaYD11YRfNUBUg2fEeiANgvJcNcxLYvScKE3eYI6ORztAGv0CxWg8fa4ylTSBc5 WPuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Th6PgAk+sHhcJGhBAXLbYoXMw1xn7ji2s1MXs2vABtU=; b=uTLY4J9fRL7+5bXFVe7q4vB+YMddlC91B0g+cIgemLZl/EKhKa0dqwvHBircRJM8tg XGYcuRh2VJrkyFqShZckME1jr4NXk4jpXm+fFIHCORwEUKGBTP79o2/RQHjoaT07pEyj CkkG8n2adWNK/z3rHSVrYTR8iEDbOo496SV10Iv1qHOUDVHY3U+0CIHjBGE+yxXYE23L GBFr+lE/GtbotCue/CgFe72TlVt2eTZEmHEAMY/ffvIxjYcG18qGPyC86TCQRWO6MaBB +w7ZcgumMlF1K91aV9qcwuCpA+kU5hmJFn5VhciTHuQ/e4AYp4Yn4BuEvd9Uhek/YIfx +Mwg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y10si13709264plt.406.2018.12.03.13.35.27; Mon, 03 Dec 2018 13:35:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726047AbeLCVf0 (ORCPT + 6 others); Mon, 3 Dec 2018 16:35:26 -0500 Received: from mail-oi1-f193.google.com ([209.85.167.193]:37559 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726069AbeLCVcg (ORCPT ); Mon, 3 Dec 2018 16:32:36 -0500 Received: by mail-oi1-f193.google.com with SMTP id y23so12372964oia.4; Mon, 03 Dec 2018 13:32:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Th6PgAk+sHhcJGhBAXLbYoXMw1xn7ji2s1MXs2vABtU=; b=BLDvSr5WFAFpCzhtpM/bfGq5YSKhc8RmPKPFjg8LFwgtLC0kGVSbHKgGECyPi03Exk zTtJyLM0kxgPfBh908XDbRYuQd+3jnbi/J/Y6pLXrcmRJvmPekIlpQGDP96D4Mu1q4k2 xMx4C/aJAvTEzVxt1vmc4OoMrwPvXr+M2sLs6KrAkIh7+BWaiWYIi/bQsEb8z7fYrzmV RcFdO5dlveRSr5hTy7Q6TYBCzoqwMx7RhswFQ5tu5NL7lZQeyuYQl6EB73uYRCeYRfIx 0aJqRAWE45fDP5WTNnjS+KT4y1uccuOoDSvS75peUdJLFqo9UX4bp3kJr4CN8FVy9dT7 UaKw== X-Gm-Message-State: AA+aEWYzI4RpcekxrnSJrDKrcsDntEoIEUBSGFEIzxnsWUZtPQ0rp14G /vZJbtfMaZ0YevypXv/u6dbisGw= X-Received: by 2002:aca:5bc3:: with SMTP id p186mr10567400oib.130.1543872755621; Mon, 03 Dec 2018 13:32:35 -0800 (PST) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id c78sm8545501oig.30.2018.12.03.13.32.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Dec 2018 13:32:34 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Sean Hudson , Frank Rowand , linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Grant Likely , Kumar Gala , arm@kernel.org, Will Deacon , Mark Rutland Subject: [PATCH v2 08/34] dt-bindings: arm: Convert PMU binding to json-schema Date: Mon, 3 Dec 2018 15:31:57 -0600 Message-Id: <20181203213223.16986-9-robh@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203213223.16986-1-robh@kernel.org> References: <20181203213223.16986-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert ARM PMU binding to DT schema format using json-schema. Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/pmu.txt | 70 -------------- .../devicetree/bindings/arm/pmu.yaml | 91 +++++++++++++++++++ 2 files changed, 91 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/pmu.txt create mode 100644 Documentation/devicetree/bindings/arm/pmu.yaml -- 2.19.1 diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt deleted file mode 100644 index 13611a8199bb..000000000000 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ /dev/null @@ -1,70 +0,0 @@ -* ARM Performance Monitor Units - -ARM cores often have a PMU for counting cpu and cache events like cache misses -and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU -representation in the device tree should be done as under:- - -Required properties: - -- compatible : should be one of - "apm,potenza-pmu" - "arm,armv8-pmuv3" - "arm,cortex-a73-pmu" - "arm,cortex-a72-pmu" - "arm,cortex-a57-pmu" - "arm,cortex-a53-pmu" - "arm,cortex-a35-pmu" - "arm,cortex-a17-pmu" - "arm,cortex-a15-pmu" - "arm,cortex-a12-pmu" - "arm,cortex-a9-pmu" - "arm,cortex-a8-pmu" - "arm,cortex-a7-pmu" - "arm,cortex-a5-pmu" - "arm,arm11mpcore-pmu" - "arm,arm1176-pmu" - "arm,arm1136-pmu" - "brcm,vulcan-pmu" - "cavium,thunder-pmu" - "qcom,scorpion-pmu" - "qcom,scorpion-mp-pmu" - "qcom,krait-pmu" -- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu - interrupt (PPI) then 1 interrupt should be specified. - -Optional properties: - -- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU - nodes corresponding directly to the affinity of - the SPIs listed in the interrupts property. - - When using a PPI, specifies a list of phandles to CPU - nodes corresponding to the set of CPUs which have - a PMU of this type signalling the PPI listed in the - interrupts property, unless this is already specified - by the PPI interrupt specifier itself (in which case - the interrupt-affinity property shouldn't be present). - - This property should be present when there is more than - a single SPI. - - -- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd - events. - -- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register - (SDER) is accessible. This will cause the driver to do - any setup required that is only possible in ARMv7 secure - state. If not present the ARMv7 SDER will not be touched, - which means the PMU may fail to operate unless external - code (bootloader or security monitor) has performed the - appropriate initialisation. Note that this property is - not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux - in Non-secure state. - -Example: - -pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <100 101>; -}; diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml new file mode 100644 index 000000000000..3ea4abfbf276 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Performance Monitor Units + +maintainers: + - Mark Rutland + - Will Deacon + +description: |+ + ARM cores often have a PMU for counting cpu and cache events like cache misses + and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU + representation in the device tree should be done as under:- + +properties: + compatible: + oneOf: + - items: + - enum: + - apm,potenza-pmu + - arm,armv8-pmuv3 + - arm,cortex-a73-pmu + - arm,cortex-a72-pmu + - arm,cortex-a57-pmu + - arm,cortex-a53-pmu + - arm,cortex-a35-pmu + - arm,cortex-a17-pmu + - arm,cortex-a15-pmu + - arm,cortex-a12-pmu + - arm,cortex-a9-pmu + - arm,cortex-a8-pmu + - arm,cortex-a7-pmu + - arm,cortex-a5-pmu + - arm,arm11mpcore-pmu + - arm,arm1176-pmu + - arm,arm1136-pmu + - brcm,vulcan-pmu + - cavium,thunder-pmu + - qcom,scorpion-pmu + - qcom,scorpion-mp-pmu + - qcom,krait-pmu + - items: + - const: arm,cortex-a7-pmu + - const: arm,cortex-a15-pmu + + interrupts: + # Don't know how many CPUs, so no constraints to specify + description: 1 per-cpu interrupt (PPI) or 1 interrupt per core. + + interrupt-affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property, unless this is already specified + by the PPI interrupt specifier itself (in which case + the interrupt-affinity property shouldn't be present). + + This property should be present when there is more than + a single SPI. + + qcom,no-pc-write: + type: boolean + description: + Indicates that this PMU doesn't support the 0xc and 0xd events. + + secure-reg-access: + type: boolean + description: + Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + +required: + - compatible + +...