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[209.132.180.67]) by mx.google.com with ESMTP id g20si20930586pgh.241.2019.01.24.00.30.44; Thu, 24 Jan 2019 00:30:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=R7WNJlIV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727568AbfAXIao (ORCPT + 7 others); Thu, 24 Jan 2019 03:30:44 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:60098 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726212AbfAXIan (ORCPT ); Thu, 24 Jan 2019 03:30:43 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0O8UaL6105748; Thu, 24 Jan 2019 02:30:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1548318636; bh=7o28m+/NAIlkSFG9m4hVjE2FfGGUC44quTmybqP8VWs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=R7WNJlIVYjc//BqL/Cdm/8oIuvZ18miyLIyIHsP3fdBbejqVRBGsBls5m8YyDiZII GzAocrFEM15EGSK/oz+YQhIyolVXGs5UGvdZr6iamVp/F4KtSXiZpquYTqrosA74qG ebPjR5XyB9jlk0jfZ5RVNYGbBN7FjpfJNcFT4M0o= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0O8UZDJ121658 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Jan 2019 02:30:36 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 24 Jan 2019 02:30:35 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 24 Jan 2019 02:30:35 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0O8UTbZ012320; Thu, 24 Jan 2019 02:30:32 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Lorenzo Pieralisi , Rob Herring CC: Bjorn Helgaas , Mark Rutland , , , , , Sekhar Nori Subject: [PATCH v3 1/3] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings Date: Thu, 24 Jan 2019 13:59:55 +0530 Message-ID: <20190124082957.29077-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190124082957.29077-1-kishon@ti.com> References: <20190124082957.29077-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new compatible strings for dra74x SoC (also used by dra76x) and dra72x. This can be used to perform SoC specific configuration (like configuring PCIe in x2 lane mode). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 452fe48c4fdd..e03d23631f5b 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -1,8 +1,12 @@ TI PCI Controllers PCIe DesignWare Controller - - compatible: Should be "ti,dra7-pcie" for RC - Should be "ti,dra7-pcie-ep" for EP + - compatible: Should be "ti,dra7-pcie" for RC (deprecated) + Should be "ti,dra7-pcie-ep" for EP (deprecated) + Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode + Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode + Should be "ti,dra726-pcie-rc" for dra72x in RC mode + Should be "ti,dra726-pcie-ep" for dra72x in EP mode - phys : list of PHY specifiers (used by generic PHY framework) - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property.