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[209.132.180.67]) by mx.google.com with ESMTP id q3si176443pfc.89.2019.05.06.03.05.58; Mon, 06 May 2019 03:05:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qPWznxSc; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726369AbfEFKF5 (ORCPT + 7 others); Mon, 6 May 2019 06:05:57 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:41149 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726362AbfEFKF5 (ORCPT ); Mon, 6 May 2019 06:05:57 -0400 Received: by mail-pf1-f193.google.com with SMTP id l132so1540728pfc.8 for ; Mon, 06 May 2019 03:05:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WKqEBPsoDpTtAdSfNyFLIMHr8olM8ej+c9mYA02GcCA=; b=qPWznxScaM12nn3xySR9qMH+ArqYqHs7zb1I5dnOfe5n17nWQ+RDgZ6egeXGBpx8jV 2PNDhNE9D6uGZM1QTq+XpdQwg/4Ly0RZWY+dFS78niW8M/RGivNwF612wMA5SI11MYCI wD1hx9RvUAA6JQJFxW52OuaNp613fGfPv1eG9jI8V4wH2wEEnWlx82lERMz+xBBbveZh 2Z7QcL4bRjkHZPTGLy3Q9dj/UWI4sqsf6qXrJy888kgl12mR4tOoxbmikstmIxoc8NYx Q/0TrWOv32gksWYxshsjOd/iz/Cv9fuavrSKL6/wZjfAu3OBhj791zT4N0g9Yhoi4Zag yu3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WKqEBPsoDpTtAdSfNyFLIMHr8olM8ej+c9mYA02GcCA=; b=paLzcOQRtNtyIjYC2F4QKln4z6lXwlXpUB7seBWdaSmHIQjg8407kU+AeAsP4cjeCp Ajtu4NAuj2Zh1cqmdzXt1Jxgv0gmUaRV0M9tURic4rNjoGAiJK8j/10rUlX18rBLua4f 9hY/fS6ULaSJ46k1kmOhdJPZg07GTJnokNdeuld8Na+7Ff/pCIKs98npUp4JAKoQ04UX gWkq+ejVm+YiAX9dFSt3jJiv+ki1GYFp242JKBrZ4Td1kTOe9A0Iaw44nprDW/4xUVya N56OscyalGdc912DUEBW31vd3qKeyLWLaGIpYnZ8SbY0H/AsLDg83x61C/gX9NSYi4Mx qtVQ== X-Gm-Message-State: APjAAAXg4bxNYOdyVMX89bQfpXisq+oN+J2GaDRndZot8zYmgb2zsbUk yOuyKE4Ih9Z7qRTmNx504ArN X-Received: by 2002:a63:9214:: with SMTP id o20mr30919321pgd.203.1557137156473; Mon, 06 May 2019 03:05:56 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:611b:55a4:e119:3b84:2d86:5b07]) by smtp.gmail.com with ESMTPSA id c137sm16229653pfb.154.2019.05.06.03.05.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 May 2019 03:05:55 -0700 (PDT) From: Manivannan Sadhasivam To: mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, robh+dt@kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loic.pallardy@st.com, Manivannan Sadhasivam Subject: [PATCH v2 2/3] ARM: dts: stm32mp157: Add missing pinctrl definitions Date: Mon, 6 May 2019 15:35:33 +0530 Message-Id: <20190506100534.24145-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190506100534.24145-1-manivannan.sadhasivam@linaro.org> References: <20190506100534.24145-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing pinctrl definitions for STM32MP157 MPU. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 75 +++++++++++++++++++++++ 1 file changed, 75 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 85c417d9983b..5efae4b4b37f 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -241,6 +241,23 @@ }; }; + i2c1_pins_b: i2c1-2 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_pins_sleep_b: i2c1-3 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ @@ -258,6 +275,21 @@ }; }; + i2c2_pins_b1: i2c2-2 { + pins { + pinmux = ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_b1: i2c2-3 { + pins { + pinmux = ; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ @@ -599,6 +631,34 @@ bias-disable; }; }; + + uart4_pins_b: uart4-1 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* UART4_RX */ + , /* UART4_CTS */ + ; /* UART4_RTS */ + bias-disable; + }; + }; }; pinctrl_z: pin-controller-z@54004000 { @@ -623,6 +683,21 @@ gpio-ranges = <&pinctrl_z 0 400 8>; }; + i2c2_pins_b2: i2c2-0 { + pins { + pinmux = ; /* I2C2_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_b2: i2c2-1 { + pins { + pinmux = ; /* I2C2_SCL */ + }; + }; + i2c4_pins_a: i2c4-0 { pins { pinmux = , /* I2C4_SCL */