From patchwork Fri Jun 21 10:53:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 167380 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp577509ilk; Fri, 21 Jun 2019 03:53:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwbGrZ9ITDUZacoHXP0PAFSu2vSl8lLQ4++jAurTmp6f7pWAltSmO0XYobraOsdL/HpHbtQ X-Received: by 2002:a17:902:42d:: with SMTP id 42mr124839519ple.228.1561114436794; Fri, 21 Jun 2019 03:53:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561114436; cv=none; d=google.com; s=arc-20160816; b=WBEbx2tlvDBJbRT+VIaSApH31JRrR8n2dYSHwIG6M4IMjN/As2JbW3xd5gU8lMkhCi HkaU5STXFmo/R1DdMwmagcv+ptnde6GhcmMovCm46hbpgXVAagWyOQ4HibtDsDljtkCJ quJ20NYRMpnW6QIgTtHZBcpFC8JKbVRfzEt0XlW1WFh+lMa13RLPfro4LXzO6JRqRdlp WYxhX9HCGwVF4gxnMQcKGqUqxSwOansMAtsDzbE23UcfaZE+95LnVeqWxGzNaeTvBlv3 kPr2Qba47yV/SPzv0/VLsvZmGlLe0D3l0CmM2rP60HTXcGr8quHXUp5wK5h1fneIBi8L LzZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=JLXwVSOGR+h70am1yo5VHpNL60vncdLe6CxLvJz2/uU=; b=v6IS/k8/MV5K4Yh37Cadx7VW9Qnq93/Oeb+y2W4P3tK2Ng0lVKUnlf/pmpL9LiThDV SmjEXYaUPvTnNIql9gT3m5FdMQczld2wWosRlnNWPlQf1nZvjavnJmrCbpI7C6zAO3Pt T0GO+CYTUldqOrJTI3sySTmEkXPluSx75Zg0ypm3QMODo7zBxT0j9W2AfUkcIDCu6meC RRue0lZ5d3lPqLU14wkLT69sfosYHYBL7CcJKDizeEJYVDppIYwt0XmaPyvFfjvgjNcc T1KeUW5VVkpfRNws4no93kLDC6j1Gyj2mEx6mu3Kt7MLRxddVY053pHaNVNSunJ3GATG S2XA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=cVsR6Y+k; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d23si2468972pjw.37.2019.06.21.03.53.56; Fri, 21 Jun 2019 03:53:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=cVsR6Y+k; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726260AbfFUKx4 (ORCPT + 8 others); Fri, 21 Jun 2019 06:53:56 -0400 Received: from conuserg-08.nifty.com ([210.131.2.75]:44254 "EHLO conuserg-08.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726218AbfFUKxz (ORCPT ); Fri, 21 Jun 2019 06:53:55 -0400 Received: from localhost.localdomain (softbank126205003112.bbtec.net [126.205.3.112]) (authenticated) by conuserg-08.nifty.com with ESMTP id x5LArK6K004596; Fri, 21 Jun 2019 19:53:21 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com x5LArK6K004596 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1561114403; bh=JLXwVSOGR+h70am1yo5VHpNL60vncdLe6CxLvJz2/uU=; h=From:To:Cc:Subject:Date:From; b=cVsR6Y+kYOxCRbyPFsK7mEEL3RrgK5J2onUmXHEoJKqV91ijwIRM+hL/4aQ0/2O2y vWuuHzjKUVK3ht3Ns496j4FuLrCttR4HB7BafpZWVTUwrJwu4jhb86bIGZkVPQLjtf P1jm+CnJHgB/mpQo3t3wWmZzUwgczMWeJU3K6whiVLHGY7g8aUb745wLHhOJ7Fer+9 0Sfh0ZzDJC8tEXRnPmC3t+3VARtbk9BvrKnQSQQcDqbTF0o2/zm70rGcG7ebHuVGAA pycnY71jxp4NQQeK3WuakO4O+FzKd+eKW5JUDwS5DVl4leV5qLedkbb5JeAbox4xyJ d/m6rcWoNzW7Q== X-Nifty-SrcIP: [126.205.3.112] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland Subject: [PATCH] ARM: dts: uniphier: update to new Denali NAND binding Date: Fri, 21 Jun 2019 19:53:16 +0900 Message-Id: <20190621105316.22201-1-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. In the new binding, the number of connected chips are described in DT instead of run-time probed. I added just one chip to the reference boards, where we do not know if the on-board NAND device is a single chip or multiple chips. If we added too many chips into DT, it would end up with the timeout error in nand_scan_ident(). I changed all the pinctrl properties to use the single CS. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld4-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-ld4.dtsi | 4 +++- arch/arm/boot/dts/uniphier-ld6b-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-pro4-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-pro4.dtsi | 2 ++ arch/arm/boot/dts/uniphier-pro5.dtsi | 4 +++- arch/arm/boot/dts/uniphier-pxs2.dtsi | 4 +++- arch/arm/boot/dts/uniphier-sld8-ref.dts | 4 ++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 4 +++- 9 files changed, 30 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts index 3aaca10f6644..f2d060f403cc 100644 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -77,4 +77,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index c2706cef0b8a..58cd4e8fa5be 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -403,9 +403,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 3d9080ee7aef..60994b6e8b99 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -90,4 +90,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 28038b17bbb3..854f2eba3e72 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -98,4 +98,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 97d051ef4968..7f64e5a616d6 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -593,6 +593,8 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 365738739412..eff74717b37c 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -458,9 +458,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 06a049f6edf8..4eddbb8d7fca 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -766,9 +766,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts index 01bf94c6b93a..cf9ea0b15065 100644 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -81,4 +81,8 @@ &nand { status = "okay"; + + nand@0 { + reg = <0>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index efce02768b6f..cbebb6e4c616 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -407,9 +407,11 @@ status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 65 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand2cs>; + pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>;