From patchwork Wed Oct 16 11:31:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 176466 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7234149ill; Wed, 16 Oct 2019 04:32:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqyGNPN3KE0G+ZLGhZncrlbABNj6tklZ1Z/4YZHaI1KFhsb9bn/UluXlQ6Ea/CrXP0I0pE1u X-Received: by 2002:aa7:d5d3:: with SMTP id d19mr37913869eds.213.1571225543509; Wed, 16 Oct 2019 04:32:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571225543; cv=none; d=google.com; s=arc-20160816; b=Py4RMNQ++opuXA1hue+apU4pwaWSUvVd4EccB8vf3KNRevNcHvEKZy+RBP/8MpB4Xc 7tvzWslqqjoX9zA8y9tZxMo76RT3mJULG1oaYWynCQSAH56rF/Xfe9MmyUU2uwXclf29 SdXHBubEh3pVC6EtPu9Wbxd86BqClNrIIYaL6bQfN+ufI+eEmS46OBlTcQIWk1pkV4QX YuryhKAuBN94EpSzSOMX/y+DVODvmnv+WzanVpG1EaPCyxF3dK3sxuCTzjn7SIykcKaN V0EMNCMV2r64rkvByKKgTIvScxpGZrIr8FFJihN5nk5kisiH1qxrEgWxQzriW4Pwx0Jj Zxzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=LaDHmzMFRFZZi0cfbucYtOjAncJhlSl2As2VSimU6go=; b=ookW1bC6vwJ4CJsYsp2W0WrW4U7I2fCLFO5Sf0Ve4j2CYDWN10iiLcAt6F6oonqsgs euC2u9FyYXxP52Vo6qYvDJAWf/kg5kfhdfJ1DA1xloJ5GoaaufOFXZcvECbMqJt6f5e1 8yuqEi6FeRG8CTihFTh6PQsD3Q5TBW6qXkQYx7ZloTpKXKKCRuCcfzBD4DRZeHFFE96+ a+jp4aN/tx3G3ZddBX3cc4XdauIfQEOrBINlL/PcTj3OeHHYOX5UDKnNb4Xx1R9InI4O AlfZRZZf99RCiZQ3T8XD360DMHg1554BR7AHNuPN7HyH/vn+23ChmiTKwhBzQ74MAxCa /nDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B2sryJVM; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y10si14948716eje.50.2019.10.16.04.32.23; Wed, 16 Oct 2019 04:32:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B2sryJVM; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405061AbfJPLcQ (ORCPT + 8 others); Wed, 16 Oct 2019 07:32:16 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:37026 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405078AbfJPLcQ (ORCPT ); Wed, 16 Oct 2019 07:32:16 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9GBWEZ7050056; Wed, 16 Oct 2019 06:32:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571225534; bh=LaDHmzMFRFZZi0cfbucYtOjAncJhlSl2As2VSimU6go=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=B2sryJVMqLWeFyw7KN7Q4ld1wlJuDrNDeA5/DWKT074d0w+X0X5677AlR6RcTqe/t zsjOv1JI5PT0H0jjaxhZW359azg4O2wbkPMQ0HkDgeTZ/ZTscScsigImosWL5crsD+ XVHRTqmtHed9VFcA3t/FPW3ZsPrO9YUeHAmDuc+E= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBWEo1081322; Wed, 16 Oct 2019 06:32:14 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 16 Oct 2019 06:32:07 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 16 Oct 2019 06:32:07 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9GBVkmF097485; Wed, 16 Oct 2019 06:32:12 -0500 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH 11/13] phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz Date: Wed, 16 Oct 2019 17:01:15 +0530 Message-ID: <20191016113117.12370-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016113117.12370-1-kishon@ti.com> References: <20191016113117.12370-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Set cmn_refclk/cmn_refclk1 frequency to 25MHz as specified in "Common Module Clock Configurations" of the Cadence Sierra 16FFC Multi-Protocol PHYPMA Specification. It is set to 25MHz since the only user of Cadence Sierra SERDES, TI J721E SoC provides input clock frequency of 100MHz. For other frequencies, cmn_refclk/cmn_refclk1 should be configured based on the "Common Module Clock Configurations". Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index dd54a0ab89b7..affede8c4368 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -196,6 +196,8 @@ struct cdns_sierra_phy { struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct clk *clk; + struct clk *cmn_refclk; + struct clk *cmn_refclk1; int nsubnodes; u32 num_lanes; bool autoconf; @@ -277,6 +279,8 @@ static int cdns_sierra_phy_init(struct phy *gphy) if (phy->autoconf) return 0; + clk_set_rate(phy->cmn_refclk, 25000000); + clk_set_rate(phy->cmn_refclk1, 25000000); if (ins->phy_type == PHY_TYPE_PCIE) { num_cmn_regs = phy->init_data->pcie_cmn_regs; num_ln_regs = phy->init_data->pcie_ln_regs; @@ -466,6 +470,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) struct resource *res; int i, ret, node = 0; void __iomem *base; + struct clk *clk; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) @@ -521,6 +526,22 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->apb_rst); } + clk = devm_clk_get_optional(dev, "cmn_refclk"); + if (IS_ERR(clk)) { + dev_err(dev, "core_ref_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1"); + if (IS_ERR(clk)) { + dev_err(dev, "core_ref_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk1 = clk; + ret = clk_prepare_enable(sp->clk); if (ret) return ret;