From patchwork Mon Oct 28 10:21:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177900 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3181411ill; Mon, 28 Oct 2019 03:22:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqz7vgcrW2P4IOsdNF9dyOz4noesz191Kt4SwlATEgeqMZBRMjea/w/+C7S2/QA/A0jr+DbG X-Received: by 2002:a17:906:6544:: with SMTP id u4mr15855110ejn.274.1572258143164; Mon, 28 Oct 2019 03:22:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572258143; cv=none; d=google.com; s=arc-20160816; b=jw9qAkDZb3Q6QESml2mWsNJvH28KqylOVo3fbxrAJGzna2yudRcD9ksI6wTt9S+pU4 dB4GAqYksBHA3HEEeah4CUGMrkilcg7640tqq2Cbtkn7IdXHhejqd6PywRTuwpTlp4jf iAsti6YoC6MskGI1YLfQ622ULlAmpMRDoHd9Jq0xGle+z2UwPy5IhK0aw/9kCzIGv0Zr MlIxhPTvu2FeKheWtNtqqDImgwlvF+TNXeKee5KDDyw/R9ADChLGMN59HpsjxmDi3Edv 3OKtt5LMh081DHBqZZbeqzIC9kvKWgBr0CvmqtwmSGW4laQl+Hx8S3ffGqulpO29Qx/f rbSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Nf1Qs7J2oXPLMu6hs54yffKkCyfxPGxqiMZcwXNIM5s=; b=Sgf/wpTI+4nhGWD6ZyPXNQw9iVvbKJaoVY6vxJz5UDIEraTfnBwjaWvVrLDONfnHWQ 5BK+LbruUsRrYBV4qXtGlWRFvniV77XRGHFUTISYSDZSA0RgYtUiAJ3b5NE5xB8RKeTl qy1vqgWVGjjMZEQcfG5uvTpmEplVG43sl+TQYdJuoaGUkdfTtFCC7cM5TQE9Pd9XC/QP dyJ41bW4SG79sL8Lh2CPPUnMLoDfe6pMhOQpI/in2uqmCSq/64abLj53fNfYEz/s9sZz +4G6SC0LIXEIejh81nLJzxi+FuHjv4XJ5reRltUdY6Ki3Df0XM7R6T0yrD1zTt5W4AoB GXgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dhCDFDoj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y67si7708928ede.436.2019.10.28.03.22.22; Mon, 28 Oct 2019 03:22:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dhCDFDoj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388208AbfJ1KWK (ORCPT + 8 others); Mon, 28 Oct 2019 06:22:10 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:47340 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732186AbfJ1KWJ (ORCPT ); Mon, 28 Oct 2019 06:22:09 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9SAM68w114584; Mon, 28 Oct 2019 05:22:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1572258126; bh=Nf1Qs7J2oXPLMu6hs54yffKkCyfxPGxqiMZcwXNIM5s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dhCDFDojXVhujpLyUAozW00lJnyV9SPShf8xvbY3e9EGi6ZHpuIWIrPhqarUm5pD1 CmQfpP887+fCiFSHdecRdht+8QYhFwkkKfc50qr74nr1SoUDM3AtkNybgdSRBiuI2M PtRMVrP/stCgGqNZymIv8p1jwcTaVcc7OnWndFwQ= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9SAM6Fm000827; Mon, 28 Oct 2019 05:22:06 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 28 Oct 2019 05:21:54 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 28 Oct 2019 05:22:06 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9SALwqH024783; Mon, 28 Oct 2019 05:22:04 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros , Rob Herring Subject: [PATCH v4 2/3] dt-bindings: phy: ti, phy-j721e-wiz: Add Type-C dir GPIO Date: Mon, 28 Oct 2019 12:21:52 +0200 Message-ID: <20191028102153.24866-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191028102153.24866-1-rogerq@ti.com> References: <20191028102153.24866-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is an optional GPIO, if specified will be used to swap lane 0 and lane 1 based on GPIO status. This is required to achieve plug flip support for USB Type-C. Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Allow the DT node to specify the time (in ms) that we need to wait before sampling the DIR line. Signed-off-by: Roger Quadros Cc: Rob Herring --- .../bindings/phy/ti,phy-j721e-wiz.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 8a1eccee6c1d..b5dcf80b8831 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -53,6 +53,23 @@ properties: assigned-clock-parents: maxItems: 2 + typec-dir-gpios: + maxItems: 1 + description: + GPIO to signal Type-C cable orientation for lane swap. + If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to + achieve the funtionality of an external type-C plug flip mux. + + typec-dir-debounce-ms: + minimum: 100 + maximum: 1000 + default: 100 + description: + Number of milliseconds to wait before sampling typec-dir-gpio. + If not specified, the default debounce of 100ms will be used. + Type-C spec states minimum CC pin debounce of 100 ms and maximum + of 200 ms. However, some solutions might need more than 200 ms. + patternProperties: "^pll[0|1]_refclk$": type: object