From patchwork Wed Feb 26 18:08:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 204175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07CA7C4BA18 for ; Wed, 26 Feb 2020 18:10:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DCD092465D for ; Wed, 26 Feb 2020 18:10:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727137AbgBZSJQ (ORCPT ); Wed, 26 Feb 2020 13:09:16 -0500 Received: from foss.arm.com ([217.140.110.172]:40454 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727097AbgBZSJQ (ORCPT ); Wed, 26 Feb 2020 13:09:16 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2F27D4B2; Wed, 26 Feb 2020 10:09:16 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D9013F881; Wed, 26 Feb 2020 10:09:14 -0800 (PST) From: Andre Przywara To: Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH 02/13] arm: dts: calxeda: Provide UART clock Date: Wed, 26 Feb 2020 18:08:50 +0000 Message-Id: <20200226180901.89940-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200226180901.89940-1-andre.przywara@arm.com> References: <20200226180901.89940-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PL011 UART binding requires two clocks to be named in a node. Add the second clock, which is the bus gate, that just gets enabled. Since this is a fixed clock anyway, it doesn't make any difference. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/ecx-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index 66ee1d34f72b..f819e3328a9e 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -114,8 +114,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xfff36000 0x1000>; interrupts = <0 20 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; + clocks = <&pclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; smic@fff3a000 {