From patchwork Wed May 13 10:29:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D56BC2D0FA for ; Wed, 13 May 2020 10:30:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E46720753 for ; Wed, 13 May 2020 10:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732472AbgEMKac (ORCPT ); Wed, 13 May 2020 06:30:32 -0400 Received: from foss.arm.com ([217.140.110.172]:42576 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKab (ORCPT ); Wed, 13 May 2020 06:30:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 433A1D6E; Wed, 13 May 2020 03:30:31 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0EFAC3F305; Wed, 13 May 2020 03:30:29 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Marc Zyngier Subject: [PATCH v3 01/20] dt-bindings: arm: gic: Allow combining arm, gic-400 compatible strings Date: Wed, 13 May 2020 11:29:57 +0100 Message-Id: <20200513103016.130417-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The arm,gic-400 compatible is probably the best matching string for the GIC in most modern SoCs, but was only introduced later into the kernel. For historic reasons and to keep compatibility, some SoC DTs were thus using a combination of this name and one of the older strings, which currently the binding denies. Add a stanza to the DT binding to allow "arm,gic-400", followed by either "arm,cortex-a15-gic" or "arm,cortex-a7-gic". This fixes binding compliance for quite some SoC .dtsi files in the kernel tree. Signed-off-by: Andre Przywara --- .../devicetree/bindings/interrupt-controller/arm,gic.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 9a47820ef346..3ab258c82930 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -39,6 +39,12 @@ properties: - qcom,msm-8660-qgic - qcom,msm-qgic2 + - items: + - const: arm,gic-400 + - enum: + - arm,cortex-a15-gic + - arm,cortex-a7-gic + - items: - const: arm,arm1176jzf-devchip-gic - const: arm,arm11mp-gic