From patchwork Thu Jul 9 23:19:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 235196 Delivered-To: patch@linaro.org Received: by 2002:a54:2c11:0:0:0:0:0 with SMTP id g17csp1638139ecp; Thu, 9 Jul 2020 16:20:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDoTo5VL0lL96uvjsngpgaYnPVai9TWKBEy+n//FqM7MmdJ7d1K/4EUrzjFCmOQh1RO4oR X-Received: by 2002:a17:906:4447:: with SMTP id i7mr48756924ejp.191.1594336819718; Thu, 09 Jul 2020 16:20:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594336819; cv=none; d=google.com; s=arc-20160816; b=BNK/s/0BSWVZvkZFCnEJKcyA+eWyC6sYHSWFz+3sj+FaRN83EUr7fWFv7NAbNUgus8 cNw4BLY2BZ5L3B6bPGr2mIh/T+o1wTdU4XFs1RSuvT3TuOGLo5ESHCoH7+a7lTnLOH8C QJMCBFHirohQf3coOtsuo0no9qzanQzB1RXYd98sHvF+PDPoyc9EWO/G/wlrc1vwkTFg 3yokbIxRFMBOzWSWFoYKnzNjaBQsYgTT+73ccMF8FNmJs+YqAUr/49bx5VKQYLsSE6U0 sJP38lfMPSBjkP6BuSbmiZJFUgNkf6kPORCOj5LADd21jWuF9Hacl+Ifloy5ajAofRmS zHCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9DEjoc4nTb8pIGGuDBB5IWvIfClSK8JgplovScBDMdE=; b=bqAeSg7d5nRXJ/H7oXhtzI5Q/LMr7mTBl03aTXSxGur7gnkzyRoqup+rgfO7kDpn57 TZgLY09FuzECeVwfiBnkacdtQPWr40PhUnVkIlsOnjMqhZ4iNdllolKhsURPtYl9Me83 o4Sh+paC3b5pu732aPhHBDpb75PkXzCVDHxqE3iy0mAqfVtUtpQZSMPCu33KSt1pf8qh TfkQQziNFRPknQ/p/ZyPJIE2eSpPMjh3YdmQXMWZXMaZ06ozh04zi/38n0O75O0Wop17 PWdgG7mEiugiWRbMx9QC59tK6NZG4kyG38geEpTDRTyLYPVU4PUvRQ+rucgVXJBlSRra doUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EI1DT7UC; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n23si2740812ejx.656.2020.07.09.16.20.19; Thu, 09 Jul 2020 16:20:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EI1DT7UC; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726852AbgGIXUR (ORCPT + 6 others); Thu, 9 Jul 2020 19:20:17 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49310 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726828AbgGIXUP (ORCPT ); Thu, 9 Jul 2020 19:20:15 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK92I122950; Thu, 9 Jul 2020 18:20:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336809; bh=9DEjoc4nTb8pIGGuDBB5IWvIfClSK8JgplovScBDMdE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EI1DT7UCQe+5y2Z2H0H3Ms6mWNwnsOmiNqNZrQfmXai4vdSHIytN+/4vgKUru0E+X O6jRE4r/LbvMpwfBOx3JInzdQCC6dTdG3DhC+TmFowc8r0pB8A2peEjX/Ty8sqohbz sxtMt354IkXx6hNSd3WjtOYa7ikHHicYe4OfEavA= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK9CA051639 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:09 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:08 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK8WX096146; Thu, 9 Jul 2020 18:20:08 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK8oc124475; Thu, 9 Jul 2020 18:20:08 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 11/13] ARM: dts: omap5-uevm: Add system timers to DSP and IPU Date: Thu, 9 Jul 2020 18:19:52 -0500 Message-ID: <20200709231954.1973-12-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The BIOS System Tick timers have been added for the IPU and DSP remoteproc devices for the OMAP5 uEVM boards. The following timers (same as the timers on OMAP4 Panda boards) are chosen: IPU : GPT3 (SMP-mode) DSP : GPT5 IPU has two Cortex-M4 processors, and is currently expected to be running in SMP-mode, so only a single timer suffices to provide the BIOS tick timer. An additional timer should be added for the second processor in IPU if it were to be run in non-SMP mode. The timer value also needs to be unique from the ones used by other processors so that they can be run simultaneously. The timers are optional, but are mandatory to support device management features such as power management and watchdog support. The above are added to successfully boot and execute firmware images configured with the respective timers, images that use internal processor subsystem timers are not affected. The timers can be changed or removed as per the system integration needs, alongside equivalent changes on the firmware side. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap5-uevm.dts | 2 ++ 1 file changed, 2 insertions(+) -- 2.26.0 diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 251885656697..bb016419ef61 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -222,9 +222,11 @@ &wlcore { &dsp { status = "okay"; memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; }; &ipu { status = "okay"; memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>; };