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[68.111.84.250]) by smtp.gmail.com with ESMTPSA id x11sm10723336pgl.65.2020.08.18.21.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2020 21:23:13 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Cc: Christian Lamparter , Florian Fainelli , Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJl?= =?utf-8?q?cki?= , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM5301X ARM ARCHITECTURE), Rob Herring , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] ARM: dts: BCM5301X: Fix pin controller node Date: Tue, 18 Aug 2020 21:23:07 -0700 Message-Id: <20200819042308.19043-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The pin controller resources start at 0xc0 from the CRU base which is at 0x100 from th DMU base, for a final address of 0x1800_c1c0, whereas we are currently off by 0x100. The resource size of the CRU is also incorrect and should end at 0x248 bytes from 0x100 which is the start address. Finally, the compatibility strings defined for the pin-controller node should reflect the SoC being used. Fixes: 9994241ac97c ("ARM: dts: BCM5301X: Describe Northstar pins mux controller") Reported-by: Christian Lamparter Signed-off-by: Florian Fainelli --- Christian, can you test this as a preliminary patch for your Cisco Meraki MR32 series? Thanks! arch/arm/boot/dts/bcm4708.dtsi | 4 ++++ arch/arm/boot/dts/bcm4709.dtsi | 4 ++++ arch/arm/boot/dts/bcm5301x.dtsi | 8 ++++---- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi index 1a19e97a987d..5064fe51e402 100644 --- a/arch/arm/boot/dts/bcm4708.dtsi +++ b/arch/arm/boot/dts/bcm4708.dtsi @@ -43,6 +43,10 @@ cpu@1 { }; +&pinctrl { + compatible = "brcm,bcm4708-pinmux"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi index e1bb8661955f..7417c275ea9d 100644 --- a/arch/arm/boot/dts/bcm4709.dtsi +++ b/arch/arm/boot/dts/bcm4709.dtsi @@ -5,6 +5,10 @@ #include "bcm4708.dtsi" +&pinctrl { + compatible = "brcm,bcm4709-pinmux"; +}; + &uart0 { clock-frequency = <125000000>; status = "okay"; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 2d9b4dd05830..bf49943f504a 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -402,14 +402,14 @@ dmu@1800c000 { cru@100 { compatible = "simple-bus"; - reg = <0x100 0x1a4>; + reg = <0x100 0x248>; ranges; #address-cells = <1>; #size-cells = <1>; - pin-controller@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; + pinctrl: pin-controller@c0 { + compatible = "brcm,bcm53012-pinmux"; + reg = <0xc0 0x24>; reg-names = "cru_gpio_control"; spi-pins {