From patchwork Tue Sep 8 16:59:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 249307 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4729656ilg; Tue, 8 Sep 2020 10:01:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzOhUl/mXzcWjn8MyeWmcC8lYyxRilF4CptpvvGtZyWd9yXAM1wy8L95oSfIW1E1btjPX6i X-Received: by 2002:a17:906:1484:: with SMTP id x4mr26364300ejc.81.1599584481457; Tue, 08 Sep 2020 10:01:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599584481; cv=none; d=google.com; s=arc-20160816; b=SAHvusDB7+nOWEDxc3djVuT09VoOHPlU5UFo4TVHe/i+KTKzFek8suY1XMuJc1FlXB xymQmT4hQ92w3EG3GDlYeugf/uOMmaQ0X12itQhy2x6VyzvotQtf1cCYhd9sSqlt+TL4 VXj6jd7FnDvWqbuZI1bX3fdnUKpw8ULYpmbFo2Plr72JD90E1xstZXilCYlTxpxFo57z d8O0fvaJb2xTYn5MOgSGuWa63tSCW0cW1JUyo1luhzGYU63RNS5OgfRWopvsEyyPPgrj 5rf36pM+VcPp+I4WtbZWr/OeBUV134hUq8AGKqn+1ti24M8dmIyHcAxss4AXCMsVRF7R fo1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=FmjuH099uiCn3rXvAwwFQmzrrjb4VVYs4/lLE60Nv/I=; b=BeyBd4sNuZeIP2spUoDYRlrmkQ7VeVxxbAd4Z7XnklA5/eJrint6szghXq5jh86eBm jrH3dDzMQRFmSH/zD2RLebJnHOKyjF2+Wvnm1M1RjQh71xCT5eZCGo5mhHUHFgKI/OUw 1I9wW6y14eZAtIKlDDc/8XhMmUOxilw4wUvnZtWfDIY/gYOHcx3Q4NoifgEsvmfq6KSN I/xjNyWBEH1rhruNApPYNBEvPU75juU+yB2VzNPb0kkh/5TJuY9ANFo2HjpMAK5dokiu ioOMY/qan/fdvluyxj6ZBWn9ny3XVzmjy4FCBBfFzIIDyctYcbmmfvO8BuzrBGa6EX8D yHdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wLd1vszn; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id by6si11778519edb.31.2020.09.08.10.01.21; Tue, 08 Sep 2020 10:01:21 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wLd1vszn; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731897AbgIHRBQ (ORCPT + 6 others); Tue, 8 Sep 2020 13:01:16 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54954 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731640AbgIHRAW (ORCPT ); Tue, 8 Sep 2020 13:00:22 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 088H0Jwn045048; Tue, 8 Sep 2020 12:00:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599584419; bh=FmjuH099uiCn3rXvAwwFQmzrrjb4VVYs4/lLE60Nv/I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wLd1vsznDaoSAfqoAKw5uf4m8BsVf2wTtxENbY85IvdHhy9iJwcg3Hv6Bepb7NXjl /uq8HIrmP1KPzWtr40fG/QeXFsDjLr5mZRkRAeBElplLmVZSlSTC95fq+qlZW54PGW OlLSd2PGepNC5PzLf0uOjXSNbszcjJBgo/qngars= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 088H0J4g082815 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Sep 2020 12:00:19 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Sep 2020 12:00:19 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Sep 2020 12:00:19 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 088H0Iwq112786; Tue, 8 Sep 2020 12:00:18 -0500 From: Grygorii Strashko To: Peter Ujfalusi , Tero Kristo , Rob Herring , Nishanth Menon , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Grygorii Strashko Subject: [PATCH v2 4/4] arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs Date: Tue, 8 Sep 2020 19:59:42 +0300 Message-ID: <20200908165942.32368-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908165942.32368-1-grygorii.strashko@ti.com> References: <20200908165942.32368-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko --- .../dts/ti/k3-j7200-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e27069317c4e..f7e6b9b5ef5f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include / { chosen { @@ -14,6 +15,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -62,3 +89,21 @@ /* UART not brought out */ status = "disabled"; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +};