From patchwork Fri Sep 18 11:21:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313178 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1225319ilg; Fri, 18 Sep 2020 04:23:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxDTOUQqTeELoDr+lGMFhkX2R/E1rJ+TJ5pT0SurZv7W3/gTo0DKGzL++RNj1BMKtlwTuYv X-Received: by 2002:a50:abc3:: with SMTP id u61mr36902919edc.129.1600428188655; Fri, 18 Sep 2020 04:23:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600428188; cv=none; d=google.com; s=arc-20160816; b=Q8sbaSbWgLZFh5hTpJs4WjCCVskxNdNidVj06XlC/ze9MD9seMIE/9wvFNWM0J+E4C vrroy7JdByr0saJrndpUY8jueOaglPt9ct//AA54lKx24cabj0pXR8uIxH8r/vSqemip 5ZfbXYmxekWb7tjdCU/Shj2pmJ+1jCjvDfw4ML+tiydjhJnK4N3Za6MRc73mKA6CYipG 35qVGuf03H2CH/l558Ama332tuZSsvI73jzf/KYkXZGx14j5kPW/NdeDx/d5BXE6WxDD tv9vs6JKZUGcBALMDUUaq92o8p3I6tGlQCsTLDH3PkF/3+Y5OC29j3ywbiIa4Oo+1p1Y UK6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=RTSWwN5wysrw426Y6GMoSbsnTHALOD9sljibBRw0yjI=; b=RcDzLbnUJVhu7VR103LUBpjR0Bm1N2Xe6ciIIfI6w5R5A9K4NkKAHWRXIIkZXIi6zM qI3K97M7jj2zU/9k8HBbNn+H6L0HnG2yZRhc80+FeJTwhjVTKwWOhbp7HNNNjnHDziv2 z0X/LwGqQCf2wNa81lCo5rtVVZnjb7/F/9AorUCYr5Uo2nqY3R4EGmSqkPpcjJK22uxQ EbRFo0Y2ej2+IvtF/h/kF51dVQdL/+/q4utF4h9De+4yTHNeO4EPYWDiX2fmXqs3kTfu 1XoffxpvWBczMw99k4XksEpZhLacs6AtY8Jz9Xa9vHSCdWOJJByFQequJuQo/6LSUUTB +OJg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a1si2012182ejk.68.2020.09.18.04.23.08; Fri, 18 Sep 2020 04:23:08 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726477AbgIRLXH (ORCPT + 6 others); Fri, 18 Sep 2020 07:23:07 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13301 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726413AbgIRLXB (ORCPT ); Fri, 18 Sep 2020 07:23:01 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 5271EADEF9CA90532B09; Fri, 18 Sep 2020 19:22:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 19:22:47 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , "Alexey Brodkin" , Vineet Gupta , devicetree , linux-snps-arc , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v5 3/6] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Fri, 18 Sep 2020 19:21:59 +0800 Message-ID: <20200918112202.3418-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918112202.3418-1-thunder.leizhen@huawei.com> References: <20200918112202.3418-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier Signed-off-by: Zhen Lei Tested-by: Haoyu Lv --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 74 ++++++++++++++++++++++++++++++++++----- 2 files changed, 67 insertions(+), 9 deletions(-) -- 1.8.3 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bfc9719dbcdc31c..7c2d1c8fa551a66 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -148,7 +148,7 @@ config DAVINCI_CP_INTC config DW_APB_ICTL bool select GENERIC_IRQ_CHIP - select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY config FARADAY_FTINTC010 bool diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index 5458004242e9d20..418183b9983dfad 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -17,6 +17,7 @@ #include #include #include +#include #define APB_INT_ENABLE_L 0x00 #define APB_INT_ENABLE_H 0x04 @@ -26,6 +27,27 @@ #define APB_INT_FINALSTATUS_H 0x34 #define APB_INT_BASE_OFFSET 0x04 +/* irq domain of the primary interrupt controller. */ +static struct irq_domain *dw_apb_ictl_irq_domain; + +static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs) +{ + struct irq_domain *d = dw_apb_ictl_irq_domain; + int n; + + for (n = 0; n < d->revmap_size; n += 32) { + struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); + u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); + + while (stat) { + u32 hwirq = ffs(stat) - 1; + + handle_domain_irq(d, hwirq, regs); + stat &= ~BIT(hwirq); + } + } +} + static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) { struct irq_domain *d = irq_desc_get_handler_data(desc); @@ -50,6 +72,30 @@ static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_map_generic_chip(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = { + .translate = irq_domain_translate_onecell, + .alloc = dw_apb_ictl_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + #ifdef CONFIG_PM static void dw_apb_ictl_resume(struct irq_data *d) { @@ -75,13 +121,20 @@ static int __init dw_apb_ictl_init(struct device_node *np, void __iomem *iobase; int ret, nrirqs, parent_irq, i; u32 reg; - const struct irq_domain_ops *domain_ops = &irq_generic_chip_ops; - - /* Map the parent interrupt for the chained handler */ - parent_irq = irq_of_parse_and_map(np, 0); - if (parent_irq <= 0) { - pr_err("%pOF: unable to parse irq\n", np); - return -EINVAL; + const struct irq_domain_ops *domain_ops; + + if (!parent || (np == parent)) { + /* It's used as the primary interrupt controller */ + parent_irq = 0; + domain_ops = &dw_apb_ictl_irq_domain_ops; + } else { + /* Map the parent interrupt for the chained handler */ + parent_irq = irq_of_parse_and_map(np, 0); + if (parent_irq <= 0) { + pr_err("%pOF: unable to parse irq\n", np); + return -EINVAL; + } + domain_ops = &irq_generic_chip_ops; } ret = of_address_to_resource(np, 0, &r); @@ -146,8 +199,13 @@ static int __init dw_apb_ictl_init(struct device_node *np, gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; } - irq_set_chained_handler_and_data(parent_irq, + if (parent_irq) { + irq_set_chained_handler_and_data(parent_irq, dw_apb_ictl_handle_irq_cascaded, domain); + } else { + dw_apb_ictl_irq_domain = domain; + set_handle_irq(dw_apb_ictl_handle_irq); + } return 0;