From patchwork Fri Sep 18 13:22:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313190 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333316ilg; Fri, 18 Sep 2020 06:23:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyP8zP2kuE9LNS2CJsClTqqB1Tu80At/2q7dtHbTKckWgvcIrZU1h0zB4pZsb1mzEM4t4wP X-Received: by 2002:a50:d2d1:: with SMTP id q17mr38639101edg.167.1600435399392; Fri, 18 Sep 2020 06:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435399; cv=none; d=google.com; s=arc-20160816; b=FnVp5LJPW1zOrhtByhKFwlFAltgLBTkciilixTgerx+yoD3qsTdckFGeXnK5qhwZGV rhPppSPN8nySe+BPTX2xRwc09pemdEsYyBSBSTL/7HivViMM4OYZOWXHpCIoYJeSnG8c oz5gA3laeGDCBLA8cY2RZ4xmhxE2HhtBLwify/Qdjh0cW3vFDjMI/rBQ5MtQcC8j5lv/ OgjbMfd56FZz4gRNWKLYxeTwQn2tpY6r0hgBDgD8AmIUIYzgc0WzwTHuihNybiQF9Ui0 0N05HHBvagi4KBK+e4XL1VIv8jIZ7bPBxmhZdKSDi4+8mrIROIiIfw9Th7vbQQPE/Z7a kOZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=nSpGz1I1JCh9AExeS5tcimKz15PuRAGKHK1yvVfhZiQ=; b=UIg4VQo3H88DuHmB4VAZaWB46mkYvYSQ/vyQ43Wyam/827mboS+HhISZEzhwwAQv3W t/CQ5qvYS9pWs7hm2fz8kEf1D/m1W3r0C5AqaGQK6jA73IOL5W6axRLFBF+I3u4KzxtP LOwXuz3wUUi3IgtOQ1+DqS8xa8WKscVVaQgLNdAf4QkaynhjTqSMCDzjIyw+3MMM5+P2 VEm5NXP1+BSaZvr9FObTd5OVsmFx+iZhY1dYwyV8OmNTGWiIn75JPBZNetvgqiJkEcV+ +q1Q5r/1rpQ7VUKG4rKlnnMxub3ZW5cVX7QXAClxvs3TT5Pfr93rtZVCAHgP6x9WRRuD JhpQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b7si2304157ejj.57.2020.09.18.06.23.19; Fri, 18 Sep 2020 06:23:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726121AbgIRNXQ (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:16 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:59476 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726786AbgIRNXQ (ORCPT ); Fri, 18 Sep 2020 09:23:16 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8C679BFC77A73522B7DA; Fri, 18 Sep 2020 21:23:13 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:04 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 9/9] dt-bindings: sp804: add support for Hisilicon sp804 timer Date: Fri, 18 Sep 2020 21:22:37 +0800 Message-ID: <20200918132237.3552-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some Hisilicon SoCs, such as Hi1212, use the Hisilicon extended sp804 timer. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/timer/arm,sp804.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.yaml b/Documentation/devicetree/bindings/timer/arm,sp804.yaml index ba0945cf799ee0b..06dfcbcc7b24255 100644 --- a/Documentation/devicetree/bindings/timer/arm,sp804.yaml +++ b/Documentation/devicetree/bindings/timer/arm,sp804.yaml @@ -15,6 +15,9 @@ description: |+ free-running mode. The input clock is shared, but can be gated and prescaled independently for each timer. + There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon + SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804". + # Need a custom select here or 'arm,primecell' will match on lots of nodes select: properties: @@ -27,7 +30,9 @@ select: properties: compatible: items: - - const: arm,sp804 + - enum: + - arm,sp804 + - hisilicon,sp804 - const: arm,primecell interrupts: