From patchwork Mon Sep 28 15:13:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313653 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393025ilg; Mon, 28 Sep 2020 08:17:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeoM1DAXdv/H1tSt95jI9kL/x3owVxNz6ev5XtW7wJHkBKJPRVBM7W1e3PB8VCwyonW4gy X-Received: by 2002:aa7:d991:: with SMTP id u17mr2332250eds.11.1601306250055; Mon, 28 Sep 2020 08:17:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306250; cv=none; d=google.com; s=arc-20160816; b=ylMSOAck4yFypsdco6++soH1hA3BkpUwI9C2nrvt8/zwR4pvWGl11xV3faRxfuWsLa Sk+yr1/G+kt7RiAnPhLXgGWSNz9i1a64rXtHF93r3sbYltQQ4qWJcnwoO2GcNQrwqGLQ gUKL6CGRvKZZL0gfQc/JhtoQrgiBriYhivnbmxNeyxCJdySmUbZsH2JIVza1WXJwQM0/ yRGNMUxar4hU3ffQpF7pPe3rLa8l0zXtiKRGQzR7NjsgnzH551rpeze0+dA7veLSIBlU i3/EaoMt8uvm3P/oBjJyvPWnGaWBxHZh1TAssA5LaWXwg2pb4xEO4EFNPVY2FFzK0SYE tVWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eP9Kk2TWGXf3Fp1/uhi3NrjPJNNPWX/aTD0AhgZAW7o=; b=fnOk5xBJYWB3cC2l9EKtGp5zMM+KahRzXlnjSt7uIkU4K4ooRkTq1iNxjgPlKC1zR+ 2NAJrf+Q7VbTV4X1BW5wDGnl1h6O6zNcB55mE5r5DH7Ij8qSSmaaWgMuUIhqEKkBHFSf e2PRhl4H8kSU+tuo9HJ9PgSXbZku6GpSoFyLpstKeXcej1C0yITiwWEHUhYSLf+L40q6 AEqagZnHSAI92aT5zO/YZKSlhXIauo9h5mwPHyTdWxlC8NqoZ1fuifR6z29g4LSr0BT2 6cm6tMw4yyF8K3velw31s6NDcbbChN3UlD/V4qpneXPuSlcvKQ7iizV97OuotlDB0res yPNA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k19si859451ejg.563.2020.09.28.08.17.29; Mon, 28 Sep 2020 08:17:30 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbgI1PR3 (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14315 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726393AbgI1PRZ (ORCPT ); Mon, 28 Sep 2020 11:17:25 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9E15D6E15112732EB426; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:13 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 06/20] ARM: dts: add SD5203 dts Date: Mon, 28 Sep 2020 23:13:10 +0800 Message-ID: <20200928151324.2134-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts -- 1.8.3 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae302..1d1262df5c55907 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000000..41113a46a71a584 --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +};