From patchwork Tue Sep 29 14:14:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313768 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206863ilg; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyc0FPUPqJYs4uLl88vj6Vm5dM4UQlmbGipLM4zQqYufVhjI/o51kg4W1CUjEvbHIcyg3T1 X-Received: by 2002:a50:9b19:: with SMTP id o25mr3360094edi.340.1601388982175; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388982; cv=none; d=google.com; s=arc-20160816; b=cZ6nVYfgGwJfF8zV1t+KTKsUWmBm8J4xzkvFIDfp8FjOlQjZ1zKcua1OQa/fleVcua J9Ph8x6/w63ZuYy0M7aNg2QmuIPhk7++QVWBYh52GiqIPpIPnlJPmcV0+THlVOiCpdVD zYPCBTrje4x+hatRdOTNtrqbLuAjzVS6mMuRDG8Lk4WCIc/NbOhByZnUjv7GaJuK5+zu 42KqWEwdN3vwe+8SRzTmoCahrY6YAjxUI7ciQ6gZr+qDLRgjI2j2JGFFmU/ZdORIE2oQ ofJIhvIfJ3fcBZnL2CFIwW7nWhCBW448FvIDzSa1WRhcwg1j4kjnbfhSO7ylXKjDhhZo I4Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=qaTY6Bs1ej95bN4jlVHPRiwBRGFpx3xoNkvxROLgOlw=; b=VZaNYuxVGRpRr/dHX38idrTD8k20NZrRk2hTrrOb9Zc12lLNetIvO2gi+NwOQKbop1 PVP0hdL9SsYZyTosYNr01e+POudJYOiCXzNqi/JbbSNYVyVNuVzWWl5LXaGgR9i1LifY SGyyYWAjS1Um+fPaxXKO91QEFY6xF+BLUCpC7tE1tn7o0vb0w5KftxAraxTwxEAATEWg fC5zQxfj0S1MZ5Q6beL4Xf1RDp31Kos6vahloDQCvJ9AH71TejnNdVu4qaXcjXAHzGqZ oStpDv/qGGBfgopGaj58Mkv/f8in8kbn/g43D6cooVLH78KKwE/2TWxRnfFtCBHPboh4 rUSA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e9si2746312ejt.529.2020.09.29.07.16.22; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730216AbgI2OQK (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:10 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14724 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730778AbgI2OPa (ORCPT ); Tue, 29 Sep 2020 10:15:30 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9F1E8884EF6EDEE079B7; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:15 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 08/17] ARM: dts: add SD5203 dts Date: Tue, 29 Sep 2020 22:14:45 +0800 Message-ID: <20200929141454.2312-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts -- 1.8.3 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae302..1d1262df5c55907 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000000..3cc9a23910be62e --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "H836ASDJ", "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +};