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[23.128.96.18]) by mx.google.com with ESMTP id n5si1403051ejk.375.2020.09.30.08.10.14; Wed, 30 Sep 2020 08:10:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NQhqVoP9; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730737AbgI3PKO (ORCPT + 6 others); Wed, 30 Sep 2020 11:10:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730707AbgI3PKN (ORCPT ); Wed, 30 Sep 2020 11:10:13 -0400 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43219C0613D2 for ; Wed, 30 Sep 2020 08:10:12 -0700 (PDT) Received: by mail-pg1-x543.google.com with SMTP id g29so1294349pgl.2 for ; Wed, 30 Sep 2020 08:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=NQhqVoP9cYIyfFnw9k09wKwqLsbH49x5IC5GDEwAcLjUdNRR5756qj3mo/pPvivvQH vfRNzsT/mBdWhClDg9f2SpHLf8rMFt7wAukhnTkVI8s4Yp64//zU6YGtYPYfvEyqcUIi xuKmtwsa+ResLjY8eIw1nDRlE2dcjlKS4AdlITloMbDOk8Rorp/YGef7ZGgPF8HGKUzI XqmRCYYLurQw1cRznFu46U+alB5k2ksrYHoOxFyeEwTN/Uc1SYiWYxSQk2KynBdpZ0ic GWi0Qxojhv7K4CPOWd9zsDB2COYYvRedcUKPzqFW58aTEJE+VxZByi4fH2FuRQBvl1Cs amzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=s/pZJ5//catQXCSLBCRVaz9Sllrw4Ti2M2QL+adl+myZ+96WOSpvW57MXjg6R4brud +dXkn172v4tdHRcql6D5uAdX+j/yWywSOSHj8Ebm7TKCn5M4pw4ynnKVIcu96HxA/jyb LwSHjdy1yyMyfjahe3JM5mLwMv96jSfnMWsqy4PEzhhhQf8MMKjlSRrQqt6b4Z1CHvT4 4hLsUjZ9eTbKHiMmw6dkapXOtI8omHNJF88jT5ll78dBGcuviZqO3tlA/8NZscMBwqJ/ ThmtpGp40+e8DHFBLGbTldsRtyK0c6meBJFMk+8MSEUT5V3JmkQV5l/t9G/5Yb4WZCCN jdZQ== X-Gm-Message-State: AOAM5303JEHEGdG1c1V5oqGf8nei/HQIbgAuyzxHWN82/1r8tRzKzqQ6 QbTH44emY+N5p4LF/G9393wr X-Received: by 2002:a65:68c4:: with SMTP id k4mr2425222pgt.18.1601478611770; Wed, 30 Sep 2020 08:10:11 -0700 (PDT) Received: from Mani-XPS-13-9360.localdomain ([2409:4072:6004:2356:f1f4:5bc8:894a:8c50]) by smtp.gmail.com with ESMTPSA id o6sm2456444pjp.33.2020.09.30.08.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2020 08:10:10 -0700 (PDT) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org Cc: svarbanov@mm-sol.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 3/5] dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC Date: Wed, 30 Sep 2020 20:39:23 +0530 Message-Id: <20200930150925.31921-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930150925.31921-1-manivannan.sadhasivam@linaro.org> References: <20200930150925.31921-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible along with the optional "atu" register region. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 02bc81bb8b2d..3b55310390a0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -13,6 +13,7 @@ - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8250" for sm8250 - reg: Usage: required @@ -27,6 +28,7 @@ - "dbi" DesignWare PCIe registers - "elbi" External local bus interface registers - "config" PCIe configuration space + - "atu" ATU address space (optional) - device_type: Usage: required @@ -131,7 +133,7 @@ - "slave_bus" AXI Slave clock -clock-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -206,7 +208,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset