From patchwork Mon Oct 5 09:31:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 314057 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1138918ilm; Mon, 5 Oct 2020 02:32:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwDpNjpHA/DjwjD3X47jpneUinuth1JEgMOQEwd2KQB1Nf0OIWDCOoD1v2sYppwoGpsBlj4 X-Received: by 2002:a17:906:f4f:: with SMTP id h15mr14343855ejj.17.1601890359326; Mon, 05 Oct 2020 02:32:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601890359; cv=none; d=google.com; s=arc-20160816; b=XSy6HatiTQMpFBlyOKRIOqki8ggP2olQThmcoMVDz6/bCIi1C04K0vfvz7rdp8EYm5 +SDvcKopGgnFyGwacPtsRurggIYoIRQKT42Nu34ps5u7GvYIz+RIhFeTmu+TXVJ1occf dFotsomd6/mDDZnk8ivNiXBFI9JKhVrVkE67Jz4Jsh2FErmKaMALbtAa1dIf1qZqsu1M EJpxRULtzaA2bZUuXO3r28HoBfZbN0TsImfM3nDyQgaDEOFM0IYgjYeAUZNccW3cqcba 8wB/gBEYLxuqioh/Z9CPv/dEihPqeO8rwNxheodDfIrab2HL3fzr/hmv/LVUG0bz1Qxk LCfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=fDI/+G6YzcRAUdfhRVHVNn6nQKZstUfu/DicpDzu+YU=; b=mTTypXf0zFQ9r6V0CPisHyBdG6K3KkxNdz0mhyfTFbjVubRGC5KeIY5J0Sudz844pE SPKFqtT4k2Eo6AlxZ5i2AaZ+kAv9UiWEoW00hTLSptKaRGPDipRz3nGCS3kgr+x0XQ11 HoZ/jbyj0APNpQEkFgzb6ggZAJKKtb4xuSUjUCZiubvr9P1GsjgxAswwg5iKFL01vAx9 fceYcNg/QX5qmRsFcHxpIFMkj80HgtivNAJy+WoXKifyHpWjR+GKlGH6X5VP8BEFjxfT jiwEAcvDCWAGpE67Z7sw+26uiM+j2AYRZJ1mH0lpSZaQ0d+73LquBQ8xnnQDqcLG2n9r fohg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DLM2CfrV; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bt4si6472783edb.130.2020.10.05.02.32.39; Mon, 05 Oct 2020 02:32:39 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DLM2CfrV; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726217AbgJEJcf (ORCPT + 6 others); Mon, 5 Oct 2020 05:32:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726352AbgJEJcf (ORCPT ); Mon, 5 Oct 2020 05:32:35 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ACE7C0613A8 for ; Mon, 5 Oct 2020 02:32:34 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id az3so2031986pjb.4 for ; Mon, 05 Oct 2020 02:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fDI/+G6YzcRAUdfhRVHVNn6nQKZstUfu/DicpDzu+YU=; b=DLM2CfrVbUiOz4tixTw3gBZP/cb2rIJjyII/tm2KLLftNsREzRcNUharWiURFgrj58 DE/I8amrrAs+AewhYphlfQINMsqW+CXdyD54n8mILe7JYetJxeqrTJax1F1zcRn9IuhT nGX/UjWufCwSy/fu7cLxkS2CXMa6m/MWWAgC5JsQ89xVN5jPL7mMydfLbgaGSwG8DAfD ZPFBvIHZMjRH0ffAf3fQI4lBsa+bMXbVsDmEUmFn8XJMLMz9IlWtDYTsVPTORGIUopLy rPWoK+B7IBuXOEAmikn7AW0TeMnP5ppzkwWmkpn8OdHZSwYvbV3o5OELRF4zMrr0PiSf 0Ekg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fDI/+G6YzcRAUdfhRVHVNn6nQKZstUfu/DicpDzu+YU=; b=LwoTtZEkccFiBkRkHjSu8nf/NjAKJ58Og90GqOHxwG96ay05vqjHxqIcn9DpnUiPmT Aunh8Lk7f4tqdxoDzlmYneG1NH3Ur6HkJjX7xm+HRt7GeW+PWhupBIirM4hZsHmD76G6 EjWieEJYNG/pFq/mrwQwVo3B6AH/Sxu0sxVOgfRteVdiz58pTFw8y1SYUeCEqp0tdZII xoEi3H5s4RWbsFTGBz+suPHEKihIB4NC4FoLB5p/vg7xt6Ibd8KN50jVSKO2NE2dfDXE nM3jxhnyXuYyc6AzHR1sjBT13d6J9tVgiZtkvgRE0Tjig0vROT2oVVTNxsVdAeiU5iIj RVaw== X-Gm-Message-State: AOAM531Ee8G6+M6FwW8flmaVQ9HLG1FOzX15LVgEZNCYf8ewp2NQlVPL uEA4tg4GodWexr7R0PW7kU/V X-Received: by 2002:a17:90a:a613:: with SMTP id c19mr16394942pjq.119.1601890353949; Mon, 05 Oct 2020 02:32:33 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id 124sm11298894pfd.132.2020.10.05.02.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2020 02:32:33 -0700 (PDT) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org Cc: svarbanov@mm-sol.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v4 4/5] PCI: qcom: Add SM8250 SoC support Date: Mon, 5 Oct 2020 15:01:51 +0530 Message-Id: <20201005093152.13489-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201005093152.13489-1-manivannan.sadhasivam@linaro.org> References: <20201005093152.13489-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the members of ops_2_7_0. The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid callback, which will be added in successive commit. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.1 Reviewed-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 3aac77a295ba..3167ad66413d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1359,6 +1359,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .post_deinit = qcom_pcie_post_deinit_2_7_0, }; +/* Qcom IP rev.: 1.9.0 */ +static const struct qcom_pcie_ops ops_1_9_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .post_init = qcom_pcie_post_init_2_7_0, + .post_deinit = qcom_pcie_post_deinit_2_7_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, }; @@ -1476,6 +1486,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { } };