From patchwork Thu Oct 8 19:14:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 317527 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1667739ilm; Thu, 8 Oct 2020 12:15:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzYk1nHVkQ0swiHoHHRF9gU1XzVH+VJYKyPEvmwYmMSHVfm+DBscTHlcnHMkSIma5n59Q9F X-Received: by 2002:a50:c309:: with SMTP id a9mr10841868edb.199.1602184513090; Thu, 08 Oct 2020 12:15:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602184513; cv=none; d=google.com; s=arc-20160816; b=gJ9NKB8nBxMcb/7y8Dgxfrsvx5ufJ/DHpKivg9xdeYNQgdcWGvlV5GhrFbu9fbJyrQ BUnj4vR473TYxeRWfnxzeNVbVnfNSXc7sIPZ4WTfdy+SEYGgZWbtu+n1L/IznA4WCv27 ivpHGcMZOj8orITe9pLSDZ7rOpVKOet7buf+B/y3klBVnW+LXd3jlSvjOtIIosjkWcVb oerKeTu1b9BgZlrJObLKUs2V69C3nsQMfuVfBCjS9R4P+V5lV40iq/BlnzK7vysYh2BB t+X0+pQ9KltV8ptkE6XoNeBOhaV29hzjM3wgBK4ijte7ECkH7uAfT9C2SWXrDQgcgR9j hC+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=76oPjUgbJRwqgwHcwk60j6uv3w0FZYuw4+zw5UdLA88=; b=IS7v3DPPS8iSth3UJZDN8jVCcOzZGAjtAG76b1/SAYxoYsJL5Ssm9sm2C09n9yKKP3 LlKtW49Dd0Hh2iZzFG+erNW2oLzmzNxtN7Atj4vTP6x0jwxN4r+ZdMC/PIGDHkFvIM0v DN4KTcsY78SU3XtuEfJt3TQb9++okqPyEJQKazweGPupOBTuGbt7Jg2BS2d68np2mOLq bMJseDMw8hB4UxE6sOcEK8zxv7TaRjFUnbMfNm0iikE5+v3sd2sCUIYWschsmqylr9W7 OuovtOcqFz0/9G1emahRXhBOKHEP7v9P+DCwD2j0z8/DffaNjBoui5B1hFgMCnAF3XVm Dfcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bw3si4437136ejb.515.2020.10.08.12.15.12; Thu, 08 Oct 2020 12:15:13 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729626AbgJHTPD (ORCPT + 6 others); Thu, 8 Oct 2020 15:15:03 -0400 Received: from foss.arm.com ([217.140.110.172]:45330 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729620AbgJHTPD (ORCPT ); Thu, 8 Oct 2020 15:15:03 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E5121529; Thu, 8 Oct 2020 12:15:03 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7B9803F70D; Thu, 8 Oct 2020 12:15:01 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH v2 2/4] dt-bindings: mailbox: add doorbell support to ARM MHU Date: Thu, 8 Oct 2020 20:14:50 +0100 Message-Id: <20201008191452.38672-3-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008191452.38672-1-sudeep.holla@arm.com> References: <20201008191452.38672-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARM MHU's reference manual states following: "The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt." This patch thus extends the MHU controller's DT binding to add support for doorbell mode. Though the same MHU hardware controller is used in the two modes, A new compatible string is added here to represent the combination of the MHU hardware and the firmware sitting on the other side (which expects each bit to represent a different signal now). Reviewed-by: Rob Herring Acked-by: Arnd Bergmann Co-developed-by: Viresh Kumar Signed-off-by: Viresh Kumar Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm,mhu.yaml | 60 +++++++++++++++++-- 1 file changed, 54 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index 2c8df7979c22..d43791a2dde7 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -18,20 +18,40 @@ description: | remote clears it after having read the data. The last channel is specified to be a 'Secure' resource, hence can't be used by Linux running NS. + The MHU hardware also allows operations in doorbell mode. The MHU drives the + interrupt signal using a 32-bit register, with all 32-bits logically ORed + together. It provides a set of registers to enable software to set, clear and + check the status of each of the bits of this register independently. The use + of 32 bits per interrupt line enables software to provide more information + about the source of the interrupt. For example, each bit of the register can + be associated with a type of event that can contribute to raising the + interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote + processor. + # We need a select here so we don't match all nodes with 'arm,primecell' select: properties: compatible: contains: - const: arm,mhu + enum: + - arm,mhu + - arm,mhu-doorbell required: - compatible properties: compatible: - items: - - const: arm,mhu - - const: arm,primecell + oneOf: + - description: Data transfer mode + items: + - const: arm,mhu + - const: arm,primecell + + - description: Doorbell mode + items: + - const: arm,mhu-doorbell + - const: arm,primecell + reg: maxItems: 1 @@ -51,8 +71,11 @@ description: | - const: apb_pclk '#mbox-cells': - description: Index of the channel. - const: 1 + description: | + Set to 1 in data transfer mode and represents index of the channel. + Set to 2 in doorbell mode and represents index of the channel and doorbell + number. + enum: [ 1, 2 ] required: - compatible @@ -63,6 +86,7 @@ description: | additionalProperties: false examples: + # Data transfer mode. - | soc { #address-cells = <2>; @@ -85,3 +109,27 @@ additionalProperties: false mboxes = <&mhuA 1>; /* HP-NonSecure */ }; }; + + # Doorbell mode. + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuB: mailbox@2b2f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scpi: scpi@2f000000 { + compatible = "arm,scpi"; + reg = <0 0x2f000000 0 0x200>; + mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + }; + };