From patchwork Mon Oct 12 06:12:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 317624 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4332711ilm; Sun, 11 Oct 2020 23:13:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxlA4Q0Sg8pqBRQr7yu5eSJCnWm6RTEPigK2UzYY5zzfA+7yNzk2Pld83UiBhP7B01KZXo8 X-Received: by 2002:aa7:c3ca:: with SMTP id l10mr12724819edr.72.1602483206002; Sun, 11 Oct 2020 23:13:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602483205; cv=none; d=google.com; s=arc-20160816; b=iRb5wTHLTMIDWs36l6ci4sE73QIA0CmOR54QX5TxQSR7m4ZGHrief/DjQB5RUTZspn 59qkBE60EQuNX8Zi/ua59wLuprgVEWWfVLMFghXfD2ZBrKDcmbC+aNtoxbQa2AvjLS/b v4AxSzi4sriGSITRyAIOkihICH4AvSgwxCZ+3pSmTixdzthxcAlBl0KXoITU9/rf3gUz u6+FRoRW5dMWR84eumjyNczMxEylhBxwYx/N/h97S+gSJAp4QCVPUx3w/2qu4f19xjNC lpgvD8QSHXz661GI6zqEbeXsUilfvMaBmc3EuHiyFHTAe3oA5CqpW2qypbY15inu3HU5 aZjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=KfltWFsZyiOR4CIPq1y3GTcU4ICQrwfgoAhMQojqfcg=; b=WXO59QDdawAzWXK5oKUVuXgBWVYRqMA7QunfxCbrWLNrCzfrQOdWTMzlT5kA1R/KW5 vAego8zCEKar99b0U4KNo7m+q3SO+W8XVNEI0f+954T1AuGzkjNf2k5H1/hpShHEEq2e 9aF/zIulFlS+3cCv+8E8dtZHiTQE0SXTiLyG5mOdCoAGnhqpAYykgghPGXaCAsGfrrpn ChDl6yQ09yLRgZmE9eMPcfHaBAL3XfwWHfoQ0dybf6AcbGgkTXN5RdEAnaYvIYh/2mZ2 GFm0+9Z25i5EQDJyu+0NCcgvrkNpMGdGOoA5nW+6NuFX0xaNTX+EkPNOsGnTFMa6MGrn Dspw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id pg3si13843761ejb.685.2020.10.11.23.13.25; Sun, 11 Oct 2020 23:13:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727225AbgJLGMs (ORCPT + 6 others); Mon, 12 Oct 2020 02:12:48 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:33566 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727199AbgJLGMr (ORCPT ); Mon, 12 Oct 2020 02:12:47 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C002F30AB600401601EA; Mon, 12 Oct 2020 14:12:45 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 14:12:36 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v2 01/10] ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml Date: Mon, 12 Oct 2020 14:12:16 +0800 Message-ID: <20201012061225.1597-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012061225.1597-1-thunder.leizhen@huawei.com> References: <20201012061225.1597-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 1. Change node name to match '^serial(@[0-9a-f,]+)*$' 2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same clock. Signed-off-by: Zhen Lei --- arch/arm/boot/dts/hip01.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/hip04-d01.dts | 2 +- arch/arm/boot/dts/hip04.dtsi | 6 +++--- 3 files changed, 16 insertions(+), 16 deletions(-) -- 1.8.3 diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 975d39828405f0b..fd09e6d9309c755 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -41,41 +41,41 @@ compatible = "simple-bus"; ranges; - uart0: uart@10001000 { + uart0: serial@10001000 { compatible = "snps,dw-apb-uart"; reg = <0x10001000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 32 4>; status = "disabled"; }; - uart1: uart@10002000 { + uart1: serial@10002000 { compatible = "snps,dw-apb-uart"; reg = <0x10002000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 33 4>; status = "disabled"; }; - uart2: uart@10003000 { + uart2: serial@10003000 { compatible = "snps,dw-apb-uart"; reg = <0x10003000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 34 4>; status = "disabled"; }; - uart3: uart@10006000 { + uart3: serial@10006000 { compatible = "snps,dw-apb-uart"; reg = <0x10006000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 4 4>; status = "disabled"; diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts index 9019e0d2ef60b67..f5691dbc26d2419 100644 --- a/arch/arm/boot/dts/hip04-d01.dts +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -22,7 +22,7 @@ }; soc { - uart0: uart@4007000 { + uart0: serial@4007000 { status = "ok"; }; }; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 555bc6b6720fc94..bccf5ba3d8553c2 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -250,12 +250,12 @@ <0 79 4>; }; - uart0: uart@4007000 { + uart0: serial@4007000 { compatible = "snps,dw-apb-uart"; reg = <0x4007000 0x1000>; interrupts = <0 381 4>; - clocks = <&clk_168m>; - clock-names = "uartclk"; + clocks = <&clk_168m>, <&clk_168m>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; status = "disabled"; };