From patchwork Tue Oct 20 20:37:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 318826 Delivered-To: patch@linaro.org Received: by 2002:a92:d1d1:0:0:0:0:0 with SMTP id u17csp1602831ilg; Tue, 20 Oct 2020 13:37:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw8yvrBFbsx6MUd4efeSzTuw6nMLACwQNyGXGJPiZAod10HurL77zmZZMp36aCRsucKvH8h X-Received: by 2002:a17:906:bc4b:: with SMTP id s11mr5122446ejv.437.1603226239828; Tue, 20 Oct 2020 13:37:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603226239; cv=none; d=google.com; s=arc-20160816; b=AeD5Of39YrU6lB+OTVYVBmOJoDXunrVjYop5XPFpP4ojDb/OGfC1XFGly8CqyDYr/L Aco3qJrA7dCJOPnXoM7/OmhCEiYsA2yl7hNV6QuOelbLTSMVBiOD8YnuwwAvIAyD8QeW rFlOjfjWAZxIBhW6i6dVhiaXLHd+9e1gEh/i9xfJK4gKcqIok/pbj9wH1LsQgTvgd8QY IytgN0WR5qkjJMAbQ/N2s3mS4gf5ZwH52BVi0YuEc/IQjFDh9/824uL548Q57LiGKjcA GwJfrAJfY2fk0lQcT0ON3YVy1A78hjkEq1PBsTUfGDL/0CspOC0smacw1wt2Va0jTE7U EYOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from; bh=/0ttUjcM7IRMBoPxBKqBzommb0EpZWttjrsG0grgmVw=; b=dxNOvIoWUmkQfL8VmnxwPYdN6LayRS9ACsIXLxFQ/A6Pw0SzrrhvMrJnqYV6RrDNX5 ricVn/4b4kIgbJPxChDrPfiimNBxEHOoFBRCGHL12jrht6HeB4mwVqPtzLhQBQ/3x3pq 0dAPAD3mYlqI68NrdcQUzmsVS6/ZPYY2+QNwC/zOmlXxOZ7zenERnR64yTqO24ZOonVB jWqeoj6nN6knnMs281CFBR7FkitANPnHD3h/Pjt0S0HvKlxIp4V3RwUH1zfF4FEJvHGg ooYCX/XT6LDsXVx5Jeu5My7/FejHm09BrF8zr78KXXPUKCfSBNF7zityNpNAzpnRfd1d yz8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h2si1937753edn.240.2020.10.20.13.37.19; Tue, 20 Oct 2020 13:37:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2409533AbgJTUhS (ORCPT + 6 others); Tue, 20 Oct 2020 16:37:18 -0400 Received: from foss.arm.com ([217.140.110.172]:55924 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2409477AbgJTUhS (ORCPT ); Tue, 20 Oct 2020 16:37:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A693331B; Tue, 20 Oct 2020 13:37:17 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BCE6C3F719; Tue, 20 Oct 2020 13:37:16 -0700 (PDT) From: Sudeep Holla To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Viresh Kumar Subject: [PATCH 1/2] dt-bindings: arm, scmi: Do not use clocks for SCMI performance domains Date: Tue, 20 Oct 2020 21:37:09 +0100 Message-Id: <20201020203710.10100-1-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit dd461cd9183f ("opp: Allow dev_pm_opp_get_opp_table() to return -EPROBE_DEFER") handles -EPROBE_DEFER for the clock/interconnects within _allocate_opp_table() which is called from dev_pm_opp_add and it now propagates the error back to the caller. SCMI performance domain re-used clock bindings to keep it simple. However with the above mentioned change, if clock property is present in a device node, opps can't be added until clk_get succeeds. So in order to fix the issue, we can register dummy clocks which is completely ugly. Since there are no upstream users for the SCMI performance domain clock bindings, let us introduce separate performance domain bindings for the same. Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,scmi.txt | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) Hi Rob/Viresh, This is actually a fix for the regression I reported here[1]. I am not adding fixes tag as I am targeting in the same release and also because it is not directly related. Regards, Sudeep [1] https://lore.kernel.org/r/20201015180555.gacdzkofpibkdn2e@bogus P.S.:/me records that this binding needs to be moved to yaml in v5.11 -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt index 55deb68230eb..0a6c1b495403 100644 --- a/Documentation/devicetree/bindings/arm/arm,scmi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scmi.txt @@ -44,7 +44,7 @@ as described in the following sections. If the platform supports dedicated mboxes, mbox-names and shmem shall be present in the sub-node corresponding to that protocol. -Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol +Clock bindings for the clocks based on SCMI Message Protocol ------------------------------------------------------------ This binding uses the common clock binding[1]. @@ -52,6 +52,19 @@ This binding uses the common clock binding[1]. Required properties: - #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. +Performance bindings for the OPPs based on SCMI Message Protocol +------------------------------------------------------------ + +Required properties: +- #perf-domain-cells: Should be 1. Contains the performance domain ID value + used by SCMI commands. + +* Property arm,scmi-perf-domain + +Devices supporting SCMI performance domain must set their "arm,scmi-perf-domain" +property with phandle to a SCMI performance domain controller followed by the +performance domain. + Power domain bindings for the power domains based on SCMI Message Protocol ------------------------------------------------------------ @@ -152,7 +165,7 @@ firmware { scmi_dvfs: protocol@13 { reg = <0x13>; - #clock-cells = <1>; + #perf-domain-cells = <1>; }; scmi_clk: protocol@14 { @@ -175,7 +188,7 @@ firmware { cpu@0 { ... reg = <0 0>; - clocks = <&scmi_dvfs 0>; + arm,scmi-perf-domain = <&scmi_dvfs 0>; }; hdlcd@7ff60000 {