From patchwork Wed Oct 21 18:31:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 318875 Delivered-To: patch@linaro.org Received: by 2002:a92:d1d1:0:0:0:0:0 with SMTP id u17csp2420359ilg; Wed, 21 Oct 2020 11:31:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyiByeiJXooNI0EtO732L/XgVU4L1cJW+oC0b3sEQtTcXwmaNZ1TPVIX2Xb3lYpFaIaoEOL X-Received: by 2002:a17:906:6bce:: with SMTP id t14mr5044628ejs.118.1603305075813; Wed, 21 Oct 2020 11:31:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603305075; cv=none; d=google.com; s=arc-20160816; b=RyNtqF33Ge5Jv0rJjPDJnfG0JMUabsN9RqyayUc1rMAMK+guGM/k0wdv/dMBCSSHCo Bcd9NIKqyQCLUL0PUmtftFeuWQPgwct2t3ZGCdL7jNmumtNE0LGTlIx/W3YMIsR/RHvV llFjdoUerbY7Gj15w1zhrk4U2FmzoJmybeTZTgvEKWg35dhD6/PVVAW/uVbHuTiJeaHY jAkBhOJZ1cywdFe9nLPw/0oEzOBtqgT9dL6KuFQKo0KzQaAxabidIlDk4618HwK2lE8z SDGC9TUmcXdc8+bidC6oGf3F37mNBqeqhZFJD1D3GesG0u6YKmiBxDa+TaA7Q1UYOTAL l0yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from; bh=hkX9gF03/CDdqROTbi7b4KcnUOGJ79kw0xQrUWS8Swk=; b=wPLbOCQnYiDBlHKu4/LWKBaGebCIzMoUddczW15cT5TKzq7+8BN+7ca9nvmasMEVG1 NvHyEGVnCjX4Ncg6vP144vNtHpl//43KVyjKnqPXb5icE6CsuCWnU34llMwwFP0BldXD WNFw4dy4z7L55HCj9kcTEF4i4ZffV97/048x1Bmp6IqN2kn0jFYATvCDhGjABjlVt7mS v4RD3VolEf21GMnWqFA2N0+d8qHXG4jzFSzsSp17atM24evU4e3KcY0QrmmlIaRMoT4t BR0ZFQo+43/vJHhRrmE7VMMNJJtViECIQ56EaVJ0MSOLs1ygtiRTY9twR5PBeCYzLWae C47Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u7si1972325edo.531.2020.10.21.11.31.15; Wed, 21 Oct 2020 11:31:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2504110AbgJUSbO (ORCPT + 6 others); Wed, 21 Oct 2020 14:31:14 -0400 Received: from foss.arm.com ([217.140.110.172]:38630 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410323AbgJUSbO (ORCPT ); Wed, 21 Oct 2020 14:31:14 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4EFF2D6E; Wed, 21 Oct 2020 11:31:13 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 56EE73F66B; Wed, 21 Oct 2020 11:31:12 -0700 (PDT) From: Sudeep Holla To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, Rob Herring , Viresh Kumar Subject: [PATCH v2 1/2] dt-bindings: arm, scmi: Do not use clocks for SCMI performance domains Date: Wed, 21 Oct 2020 19:31:03 +0100 Message-Id: <20201021183104.27949-1-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit dd461cd9183f ("opp: Allow dev_pm_opp_get_opp_table() to return -EPROBE_DEFER") handles -EPROBE_DEFER for the clock/interconnects within _allocate_opp_table() which is called from dev_pm_opp_add and it now propagates the error back to the caller. SCMI performance domain re-used clock bindings to keep it simple. However with the above mentioned change, if clock property is present in a device node, opps can't be added until clk_get succeeds. So in order to fix the issue, we can register dummy clocks which is completely ugly. Since there are no upstream users for the SCMI performance domain clock bindings, let us introduce separate performance domain bindings for the same. Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,scmi.txt | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) v1[1]->v2: - Changed the generic #perf-domain-cells to more SCMI specific property #arm,scmi-perf-domain-cells Hi Rob/Viresh, This is actually a fix for the regression I reported here[2]. I am not adding fixes tag as I am targeting in the same release and also because it is not directly related. Regards, Sudeep [1] https://lore.kernel.org/r/20201020203710.10100-1-sudeep.holla@arm.com [2] https://lore.kernel.org/r/20201015180555.gacdzkofpibkdn2e@bogus P.S.:/me records that this binding needs to be moved to yaml in v5.11 -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt index 55deb68230eb..7af1be54f6c7 100644 --- a/Documentation/devicetree/bindings/arm/arm,scmi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scmi.txt @@ -44,7 +44,7 @@ as described in the following sections. If the platform supports dedicated mboxes, mbox-names and shmem shall be present in the sub-node corresponding to that protocol. -Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol +Clock bindings for the clocks based on SCMI Message Protocol ------------------------------------------------------------ This binding uses the common clock binding[1]. @@ -52,6 +52,19 @@ This binding uses the common clock binding[1]. Required properties: - #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. +Performance bindings for the OPPs based on SCMI Message Protocol +------------------------------------------------------------ + +Required properties: +- #arm,scmi-perf-domain-cells: Should be 1. Contains the performance domain ID + value used by SCMI commands. + +* Property arm,scmi-perf-domain + +Devices supporting SCMI performance domain must set their "arm,scmi-perf-domain" +property with phandle to a SCMI performance domain controller followed by the +performance domain. + Power domain bindings for the power domains based on SCMI Message Protocol ------------------------------------------------------------ @@ -152,7 +165,7 @@ firmware { scmi_dvfs: protocol@13 { reg = <0x13>; - #clock-cells = <1>; + #arm,scmi-perf-domain-cells = <1>; }; scmi_clk: protocol@14 { @@ -175,7 +188,7 @@ firmware { cpu@0 { ... reg = <0 0>; - clocks = <&scmi_dvfs 0>; + arm,scmi-perf-domain = <&scmi_dvfs 0>; }; hdlcd@7ff60000 {