diff mbox series

[v3,06/11] dt-bindings: phy: convert HDMI PHY binding to YAML schema

Message ID 20201118082126.42701-6-chunfeng.yun@mediatek.com
State Superseded
Headers show
Series [v3,01/11] dt-bindings: usb: convert usb-device.txt to YAML schema | expand

Commit Message

Chunfeng Yun (云春峰) Nov. 18, 2020, 8:21 a.m. UTC
Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml

Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v3: add Reviewed-by Rob
v2: fix binding check warning of reg in example
---
 .../display/mediatek/mediatek,hdmi.txt        | 18 +---
 .../bindings/phy/mediatek,hdmi-phy.yaml       | 91 +++++++++++++++++++
 2 files changed, 92 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

Comments

Chunfeng Yun (云春峰) Nov. 20, 2020, 2:25 a.m. UTC | #1
On Fri, 2020-11-20 at 07:42 +0800, Chun-Kuang Hu wrote:
> Hi, Chunfeng:

> 

> Chunfeng Yun <chunfeng.yun@mediatek.com> 於 2020年11月18日 週三 下午4:21寫道:

> >

> > Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml

> >

> > Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>

> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

> > Reviewed-by: Rob Herring <robh@kernel.org>

> > ---

> > v3: add Reviewed-by Rob

> > v2: fix binding check warning of reg in example

> > ---

> >  .../display/mediatek/mediatek,hdmi.txt        | 18 +---

> >  .../bindings/phy/mediatek,hdmi-phy.yaml       | 91 +++++++++++++++++++

> >  2 files changed, 92 insertions(+), 17 deletions(-)

> >  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

> >

> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt

> > index 6b1c586403e4..b284ca51b913 100644

> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt

> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt

> > @@ -53,23 +53,7 @@ Required properties:

> >

> >  HDMI PHY

> >  ========

> > -

> > -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel

> > -output and drives the HDMI pads.

> > -

> > -Required properties:

> > -- compatible: "mediatek,<chip>-hdmi-phy"

> > -- the supported chips are mt2701, mt7623 and mt8173

> > -- reg: Physical base address and length of the module's registers

> > -- clocks: PLL reference clock

> > -- clock-names: must contain "pll_ref"

> > -- clock-output-names: must be "hdmitx_dig_cts" on mt8173

> > -- #phy-cells: must be <0>

> > -- #clock-cells: must be <0>

> > -

> > -Optional properties:

> > -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa

> > -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c

> > +See phy/mediatek,hdmi-phy.yaml

> >

> >  Example:

> >

> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

> > new file mode 100644

> > index 000000000000..96700bb8bc00

> > --- /dev/null

> > +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

> > @@ -0,0 +1,91 @@

> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> > +# Copyright (c) 2020 MediaTek

> > +%YAML 1.2

> > +---

> > +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#

> > +$schema: http://devicetree.org/meta-schemas/core.yaml#

> > +

> > +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding

> > +

> > +maintainers:

> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>

> > +  - Chunfeng Yun <chunfeng.yun@mediatek.com>

> 

> Please add Philipp Zabel because he is Mediatek DRM driver maintainer.

Ok, will do it

Thanks a lot

> 

> DRM DRIVERS FOR MEDIATEK

> M: Chun-Kuang Hu <chunkuang.hu at kernel.org>

> M: Philipp Zabel <p.zabel at pengutronix.de>

> L: dri-devel at lists.freedesktop.org

> S: Supported

> F: Documentation/devicetree/bindings/display/mediatek/

> 

> Regards,

> Chun-Kuang.

> 

> > +

> > +description: |

> > +  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel

> > +  output and drives the HDMI pads.

> > +

> > +properties:

> > +  $nodename:

> > +    pattern: "^hdmi-phy@[0-9a-f]+$"

> > +

> > +  compatible:

> > +    enum:

> > +      - mediatek,mt2701-hdmi-phy

> > +      - mediatek,mt7623-hdmi-phy

> > +      - mediatek,mt8173-hdmi-phy

> > +

> > +  reg:

> > +    maxItems: 1

> > +

> > +  clocks:

> > +    items:

> > +      - description: PLL reference clock

> > +

> > +  clock-names:

> > +    items:

> > +      - const: pll_ref

> > +

> > +  clock-output-names:

> > +    items:

> > +      - const: hdmitx_dig_cts

> > +

> > +  "#phy-cells":

> > +    const: 0

> > +

> > +  "#clock-cells":

> > +    const: 0

> > +

> > +  mediatek,ibias:

> > +    description:

> > +      TX DRV bias current for < 1.65Gbps

> > +    $ref: /schemas/types.yaml#/definitions/uint32

> > +    minimum: 0

> > +    maximum: 63

> > +    default: 0xa

> > +

> > +  mediatek,ibias_up:

> > +    description:

> > +      TX DRV bias current for >= 1.65Gbps

> > +    $ref: /schemas/types.yaml#/definitions/uint32

> > +    minimum: 0

> > +    maximum: 63

> > +    default: 0x1c

> > +

> > +required:

> > +  - compatible

> > +  - reg

> > +  - clocks

> > +  - clock-names

> > +  - clock-output-names

> > +  - "#phy-cells"

> > +  - "#clock-cells"

> > +

> > +additionalProperties: false

> > +

> > +examples:

> > +  - |

> > +    #include <dt-bindings/clock/mt8173-clk.h>

> > +    hdmi_phy: hdmi-phy@10209100 {

> > +        compatible = "mediatek,mt8173-hdmi-phy";

> > +        reg = <0x10209100 0x24>;

> > +        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;

> > +        clock-names = "pll_ref";

> > +        clock-output-names = "hdmitx_dig_cts";

> > +        mediatek,ibias = <0xa>;

> > +        mediatek,ibias_up = <0x1c>;

> > +        #clock-cells = <0>;

> > +        #phy-cells = <0>;

> > +    };

> > +

> > +...

> > --

> > 2.18.0

> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
index 6b1c586403e4..b284ca51b913 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -53,23 +53,7 @@  Required properties:
 
 HDMI PHY
 ========
-
-The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
-output and drives the HDMI pads.
-
-Required properties:
-- compatible: "mediatek,<chip>-hdmi-phy"
-- the supported chips are mt2701, mt7623 and mt8173
-- reg: Physical base address and length of the module's registers
-- clocks: PLL reference clock
-- clock-names: must contain "pll_ref"
-- clock-output-names: must be "hdmitx_dig_cts" on mt8173
-- #phy-cells: must be <0>
-- #clock-cells: must be <0>
-
-Optional properties:
-- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
-- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+See phy/mediatek,hdmi-phy.yaml
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
new file mode 100644
index 000000000000..96700bb8bc00
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
@@ -0,0 +1,91 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Chunfeng Yun <chunfeng.yun@mediatek.com>
+
+description: |
+  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+  output and drives the HDMI pads.
+
+properties:
+  $nodename:
+    pattern: "^hdmi-phy@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - mediatek,mt2701-hdmi-phy
+      - mediatek,mt7623-hdmi-phy
+      - mediatek,mt8173-hdmi-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: PLL reference clock
+
+  clock-names:
+    items:
+      - const: pll_ref
+
+  clock-output-names:
+    items:
+      - const: hdmitx_dig_cts
+
+  "#phy-cells":
+    const: 0
+
+  "#clock-cells":
+    const: 0
+
+  mediatek,ibias:
+    description:
+      TX DRV bias current for < 1.65Gbps
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 63
+    default: 0xa
+
+  mediatek,ibias_up:
+    description:
+      TX DRV bias current for >= 1.65Gbps
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 63
+    default: 0x1c
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - clock-output-names
+  - "#phy-cells"
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8173-clk.h>
+    hdmi_phy: hdmi-phy@10209100 {
+        compatible = "mediatek,mt8173-hdmi-phy";
+        reg = <0x10209100 0x24>;
+        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+        clock-names = "pll_ref";
+        clock-output-names = "hdmitx_dig_cts";
+        mediatek,ibias = <0xa>;
+        mediatek,ibias_up = <0x1c>;
+        #clock-cells = <0>;
+        #phy-cells = <0>;
+    };
+
+...