From patchwork Fri Dec 4 01:42:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 337700 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp784509ilb; Thu, 3 Dec 2020 17:45:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJy8P+cGsyDhZua3XSMb5MpvMWaCePBj2cx2S6RF+0odeeiY+AOoWfeVBnTpggK/NO6gO+uJ X-Received: by 2002:a50:e715:: with SMTP id a21mr5444985edn.285.1607046331398; Thu, 03 Dec 2020 17:45:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607046331; cv=none; d=google.com; s=arc-20160816; b=hALpW98uMAjDJ/EPOsSFuM+2ABsjU2+rSevJ8lvMKtH3Rs67rQN93LtKgQ5CyOZHxW HRKVLbuhhSVjDU3YU16uw1lSprqjYGaoPZdKF6PEo/Qa7umDBMeb5Ari0Yv4X+HMxuXG RoawkSICvzM7XtYvCItEZiphMOCAE2+3AyS/7/cwkBpM1kLiI1haJ88gb4vdDGkXyEQ0 2o2vC7OtziGG7BrHyxXufW8McFATZqHauffMOLVSs4UKwjvt1PpwWAZIvz16VB6JMHF2 ug9RISwmi9vGATqGBhS4+CpfJFkxUJVtENw6A0O9DhaNDm3OqPyys5Kj8UOkphA6V8xl TLuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=owX/PhfbcFJeWJ3EwGDTBI4JtcpUNpABMw5bsHZWjEw=; b=vlRjQe0dGz8wrO3vlTsNSIHoG14gVyaaOYVlOHE/OOX5ulsrsVKVaL7okPwM7qnreJ ou5NlVobJ2VZI+BuJZmHt7gQFP4g3QuXJjnk/WtN/2cfZVXrUnl5cpnSfyby/B9PpEIY bZyOLTAbGu1u8nMIWKrvXtC4ffeJIJACntXjSxM2LL7ewWPCmmChu/UOlVAcDXW4LIEa hDaYFGArkhjkgRcs53LTmhDvIXDWyDFUAvaHC/36Rmo7XsMotrbadoytSvxyHLGWUN0m ZmaD1jyXr1G0I7+t1MkT9mbYH6tNm0ou9JH6feJzyI+tu/DM6f4eEGmiCG6ygoU35B8d /pRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hq6si479351ejc.40.2020.12.03.17.45.31; Thu, 03 Dec 2020 17:45:31 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726443AbgLDBny (ORCPT + 6 others); Thu, 3 Dec 2020 20:43:54 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:8640 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725849AbgLDBnx (ORCPT ); Thu, 3 Dec 2020 20:43:53 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CnFnq0qzyz15WJn; Fri, 4 Dec 2020 09:42:39 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.9) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Fri, 4 Dec 2020 09:42:56 +0800 From: Zhen Lei To: Philipp Zabel , Wei Xu , "Rob Herring" , linux-arm-kernel , devicetree , linux-kernel CC: Zhen Lei , Zhangfei Gao , Chen Feng , "Manivannan Sadhasivam" Subject: [PATCH v2 3/3] dt-bindings: reset: convert Hisilicon reset controller bindings to json-schema Date: Fri, 4 Dec 2020 09:42:36 +0800 Message-ID: <20201204014236.1158-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201204014236.1158-1-thunder.leizhen@huawei.com> References: <20201204014236.1158-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.9] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon reset controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../bindings/reset/hisilicon,hi3660-reset.txt | 44 ------------- .../bindings/reset/hisilicon,hi3660-reset.yaml | 77 ++++++++++++++++++++++ 2 files changed, 77 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt deleted file mode 100644 index aefd26710f9e87d..000000000000000 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt +++ /dev/null @@ -1,44 +0,0 @@ -Hisilicon System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller registers are part of the system-ctl block on -hi3660 and hi3670 SoCs. - -Required properties: -- compatible: should be one of the following: - "hisilicon,hi3660-reset" for HI3660 - "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670 -- hisilicon,rst-syscon: phandle of the reset's syscon. -- #reset-cells : Specifies the number of cells needed to encode a - reset source. The type shall be a and the value shall be 2. - - Cell #1 : offset of the reset assert control - register from the syscon register base - offset + 4: deassert control register - offset + 8: status control register - Cell #2 : bit position of the reset in the reset control register - -Example: - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3660-iomcu", "syscon"; - reg = <0x0 0xffd7e000 0x0 0x1000>; - }; - - iomcu_rst: iomcu_rst_controller { - compatible = "hisilicon,hi3660-reset"; - hisilicon,rst-syscon = <&iomcu>; - #reset-cells = <2>; - }; - -Specifying reset lines connected to IP modules -============================================== -example: - - i2c0: i2c@..... { - ... - resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */ - ... - }; diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml new file mode 100644 index 000000000000000..9bf40952e5b7d28 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon System Reset Controller + +maintainers: + - Wei Xu + +description: | + Please also refer to reset.txt in this directory for common reset + controller binding usage. + The reset controller registers are part of the system-ctl block on + hi3660 and hi3670 SoCs. + +properties: + compatible: + oneOf: + - items: + - const: hisilicon,hi3660-reset + - items: + - const: hisilicon,hi3670-reset + - const: hisilicon,hi3660-reset + + hisilicon,rst-syscon: + description: phandle of the reset's syscon. + $ref: /schemas/types.yaml#/definitions/phandle + + '#reset-cells': + description: | + Specifies the number of cells needed to encode a reset source. + Cell #1 : offset of the reset assert control register from the syscon + register base + offset + 4: deassert control register + offset + 8: status control register + Cell #2 : bit position of the reset in the reset control register + const: 2 + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + #include + #include + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0xffd7e000 0x1000>; + }; + + iomcu_rst: iomcu_rst_controller { + compatible = "hisilicon,hi3660-reset"; + hisilicon,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + + /* Specifying reset lines connected to IP modules */ + i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0xffd71000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; +...