From patchwork Fri Jan 22 08:36:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 369610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44504C433E0 for ; Fri, 22 Jan 2021 08:39:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F171E235F9 for ; Fri, 22 Jan 2021 08:39:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726024AbhAVIjM (ORCPT ); Fri, 22 Jan 2021 03:39:12 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:52457 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727105AbhAVIhq (ORCPT ); Fri, 22 Jan 2021 03:37:46 -0500 X-UUID: d7790b7198b84e9997d0567646afedae-20210122 X-UUID: d7790b7198b84e9997d0567646afedae-20210122 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 679792100; Fri, 22 Jan 2021 16:36:40 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Jan 2021 16:36:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Jan 2021 16:36:38 +0800 From: Stanley Chu To: , , , , , , , CC: , , , , , , , , , , , , Stanley Chu Subject: [PATCH v3 2/2] arm64: dts: mt6779: Support ufshci and ufsphy Date: Fri, 22 Jan 2021 16:36:27 +0800 Message-ID: <20210122083627.2893-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210122083627.2893-1-stanley.chu@mediatek.com> References: <20210122083627.2893-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Support UFS on MT6779 platforms by adding ufshci and ufsphy nodes in dts file. Reviewed-by: Hanks Chen Signed-off-by: Stanley Chu --- arch/arm64/boot/dts/mediatek/mt6779.dtsi | 36 +++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 370f309d32de..6eaf230bb0d1 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -225,6 +225,41 @@ #clock-cells = <1>; }; + ufshci: ufshci@11270000 { + compatible = "mediatek,mt8183-ufshci"; + reg = <0 0x11270000 0 0x2300>; + interrupts = ; + phys = <&ufsphy>; + + clocks = <&infracfg_ao CLK_INFRA_UFS>, + <&infracfg_ao CLK_INFRA_UFS_TICK>, + <&infracfg_ao CLK_INFRA_UFS_AXI>, + <&infracfg_ao CLK_INFRA_UNIPRO_TICK>, + <&infracfg_ao CLK_INFRA_UNIPRO_MBIST>, + <&topckgen CLK_TOP_FAES_UFSFDE>, + <&infracfg_ao CLK_INFRA_AES_UFSFDE>, + <&infracfg_ao CLK_INFRA_AES_BCLK>; + clock-names = "ufs", "ufs_tick", "ufs_axi", + "unipro_tick", "unipro_mbist", + "aes_top", "aes_infra", "aes_bclk"; + freq-table-hz = <0 0>, <0 0>, <0 0>, + <0 0>, <0 0>, <0 0>, + <0 0>, <0 0>; + + mediatek,ufs-disable-ah8; + mediatek,ufs-support-va09; + }; + + ufsphy: phy@11fa0000 { + compatible = "mediatek,mt8183-ufsphy"; + reg = <0 0x11fa0000 0 0xc000>; + #phy-cells = <0>; + + clocks = <&infracfg_ao CLK_INFRA_UNIPRO_SCK>, + <&infracfg_ao CLK_INFRA_UFS_MP_SAP_BCLK>; + clock-names = "unipro", "mp"; + }; + mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt6779-mfgcfg", "syscon"; reg = <0 0x13fbf000 0 0x1000>; @@ -266,6 +301,5 @@ reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; - }; };