From patchwork Fri Jan 22 10:51:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 369600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 899B1C43381 for ; Fri, 22 Jan 2021 10:57:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4EE742246B for ; Fri, 22 Jan 2021 10:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727069AbhAVK5r (ORCPT ); Fri, 22 Jan 2021 05:57:47 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:12636 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726951AbhAVKwY (ORCPT ); Fri, 22 Jan 2021 05:52:24 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10MAmG88002482; Fri, 22 Jan 2021 11:51:30 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=KBEHlzZfeXt0Wny9pLnYEhapcASdkiKxPZRpUa+smeo=; b=eZu+HmaZtIOk24w1Qay5MT808V/QD2Pdys1gK5AfSBD08loniUXLF+wc64l78X7M2H1I Vv1o+4RK/R192ZAEgR9/cWfR0Q15Bn1DLDNw22cJcz5n7hC2LhSxVLmKsm5szl2bJi68 Du6EauAbFby/2Nxx5U7YlSrjbFCIJfDYJkcazKuD9Qc2EUWcUkQLYIULUVN0uSBrAdAp dRqtkp3DoL0qSqz0WWZbb9epafIcbG2ThGy31k62Skl8x0YenCQPUq3CZ0wA4PZiwKU8 erxWU5pqpDAN9tINn96KdQ3w3iZwxhIxR86+cYO6LoCmBmC83y8cUXLP0LPREu6G8WlN yw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 3668pqhdvh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Jan 2021 11:51:30 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E0FC8100034; Fri, 22 Jan 2021 11:51:28 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D2C4D22DBCA; Fri, 22 Jan 2021 11:51:28 +0100 (CET) Received: from localhost (10.75.127.51) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 22 Jan 2021 11:51:28 +0100 From: To: Michael Turquette , Stephen Boyd , Rob Herring , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Etienne Carriere , Gabriel Fernandez CC: , , , , Subject: [PATCH 14/14] ARM: dts: stm32: introduce basic boot include on stm32mp15x board Date: Fri, 22 Jan 2021 11:51:01 +0100 Message-ID: <20210122105101.27374-15-gabriel.fernandez@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210122105101.27374-1-gabriel.fernandez@foss.st.com> References: <20210122105101.27374-1-gabriel.fernandez@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-22_06:2021-01-21,2021-01-22 signatures=0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Gabriel Fernandez Include this .dtsi file to be backward compatible with old basic bootchain. For example add: #include "stm32mp15-no-scmi.dtsi" in a stm32mp157c*.dts file. Signed-off-by: Gabriel Fernandez --- arch/arm/boot/dts/stm32mp15-no-scmi.dtsi | 158 +++++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi diff --git a/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi new file mode 100644 index 000000000000..4939f96da739 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +/ { + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + cpus { + cpu0: cpu@0 { + clocks = <&rcc CK_MPU>; + }; + + cpu1: cpu@1 { + clocks = <&rcc CK_MPU>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x404>; + mask = <0x1>; + }; + + soc { + m_can1: can@4400e000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + m_can2: can@4400f000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + cryp1: cryp@54001000 { + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + }; + + dsi: dsi@5a000000 { + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + }; + }; + + ahb { + m4_rproc: m4@10000000 { + resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; + + m4_system_resources { + m4_cec: cec@40016000 { + clocks = <&rcc CEC_K>, <&rcc CK_LSE>; + }; + + m4_m_can1: can@4400e000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + m4_m_can2: can@4400f000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + }; + }; + }; + + firmware { + /delete-node/ scmi0; + /delete-node/ scmi1; + }; + /delete-node/ sram@2ffff000; +}; + +&cec { + clocks = <&rcc CEC_K>, <&clk_lse>; +}; + +&gpioz { + clocks = <&rcc GPIOZ>; +}; + +&hash1 { + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; +}; + +&i2c4 { + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; +}; + +&i2c6 { + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; +}; + +&mdma1 { + clocks = <&rcc MDMA>; + resets = <&rcc MDMA_R>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc", "syscon"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; +}; + +&rng1 { + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; +}; + +&rtc { + clocks = <&rcc RTCAPB>, <&rcc RTC>; +}; + +&spi6 { + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; +}; + +&usart1 { + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; +};