From patchwork Wed Jan 27 07:08:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371483 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp4944jam; Tue, 26 Jan 2021 23:13:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJzlHLgSxTuwMbor9ADcX/vmkoNH8Qd4mMsQUW77cnk5JMJkRv9/LLBspZIN5AUFGCyLZ4Aj X-Received: by 2002:a17:906:1308:: with SMTP id w8mr5715306ejb.396.1611731611979; Tue, 26 Jan 2021 23:13:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611731611; cv=none; d=google.com; s=arc-20160816; b=cpYO3hvYmpLayR4jSCHCxyuKJbbJjt38Zqw+00vYJmapnZ+3OOI6lJLKI5H/llNsUT RiwEPvVoiYZ0B3Al7eVmkmraPj1SSAlGcbN7GSjDYdNi84SYAWREiQ+D/UfyJ1K0Lb+c temNfNNq7LSL5MWbI1OZ7xR0avfBRB3lel/ZpRpLYbdyyHxff25TdczobfNhYka/sfxT AGlABijpeK6OlqsEXUc4b2huNgNEePBFK41JdKkpjeCIq3BuaukSBIb3ILfXep0+Da9w uOeZeOM/ruMTlmwMd5hrPadK70FTwkq6eVssUuhdJ1M46OkHlbABeVQmiXIVDDfg865L MaRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yj0WAkoP4UOGqJx3P5rMli4eL0Z2hrMqINfywNe6bco=; b=kDJfPOGBAJBAQ11S2l9xoj167jgc9kmick2hFpOLfgPQ2i+/smXGnoN2+M/nl7AxmF Lb9V8bk26xsLLQIX73GIW0thFmi6xVnWxjHr+MqZDA4ppQeMY1AfpvBI6hwMB+Fd6TQ7 PjF6d+IeksTToCouW5Yqvs5DP+iG5gKqgB6/5910rpaiZjDgzzlvKgMOu9K/0isf20z2 /LxSoKLp0cKJBgKOYaYVw/JWYUO6Ifwkf0L04u6mWww67rqzlf0HzX4xKnIoDV5tfdlj nq2z/teKsM5KNlOvl4XNUnSsUa0SZu7RAw4FK5uuhRNErk1U5e1L/jsyzRXm4332JA1u Kfag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=gOsLXmfN; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ga16si463787ejc.412.2021.01.26.23.13.31; Tue, 26 Jan 2021 23:13:31 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=gOsLXmfN; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233184AbhA0HMu (ORCPT + 6 others); Wed, 27 Jan 2021 02:12:50 -0500 Received: from mail.kernel.org ([198.145.29.99]:45540 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232374AbhA0HJL (ORCPT ); Wed, 27 Jan 2021 02:09:11 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7D6A62072C; Wed, 27 Jan 2021 07:08:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611731310; bh=Y4lin5XW4XbmWUCOFnuEYMKBivSBkDGA8LTHpmbqjt4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gOsLXmfN/8aQA5vyCACsv1TumBxIHBZqBiCWPlzaAH31r128LArLvoBcc8sl+hBqJ MYOatMtMP0wRX83FLfxpXLBvGoYB8MIz1Mnsym0ERXABJbB8X+AzrcXiiaHT7/ZMad 8QkloYe4iYiYnjwJICLCd7hogpxnVgULKGkt/XzdRiRtJJ8qdXonL4bdpbyMvuHZRC IlSRqaCx0ArFaVyHMN7W0M5tWfpb74vgvAyri20/Yc33L+7JgA0j0lxsmxNuyg8fFr ozh1jjNW4tzQxQLkNw60z3HVoN4TWmBiWKMnm42nwGOpfbExikQW14aV1whXikdwdW n7LbCEj/MYQ+g== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/5] clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate() Date: Wed, 27 Jan 2021 12:38:08 +0530 Message-Id: <20210127070811.152690-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210127070811.152690-1-vkoul@kernel.org> References: <20210127070811.152690-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but with different registers. Modularize these by moving out latch and latch ack bits so that we can reuse the function. Suggested-by: AngeloGioacchino Del Regno Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) -- 2.26.2 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f7721088494c..a30ea7b09224 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1471,8 +1471,8 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); } -static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) +static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate, u32 latch_bit, u32 latch_ack) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); unsigned long rrate; @@ -1490,22 +1490,20 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); /* Latch the PLL input */ - ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), - PLL_UPDATE, PLL_UPDATE); + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); if (ret) return ret; /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); - if (!(val & ALPHA_PLL_ACK_LATCH)) { + if (!(val & latch_ack)) { pr_err("Lucid PLL latch failed. Output may be unstable!\n"); return -EINVAL; } /* Return the latch input to 0 */ - ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), - PLL_UPDATE, 0); + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); if (ret) return ret; @@ -1520,6 +1518,12 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); +} + const struct clk_ops clk_alpha_pll_trion_ops = { .prepare = alpha_pll_trion_prepare, .enable = clk_trion_pll_enable,