From patchwork Thu Mar 4 04:41:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 392726 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp348650jai; Thu, 4 Mar 2021 14:16:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJzgbu0F2T8K31yEKWecDiLW+jM0kVh/HjCK5ZaHtwxKBKvPprZMIvjUYrkkS0vecOEHeJpu X-Received: by 2002:a05:6402:3550:: with SMTP id f16mr6616502edd.134.1614896188450; Thu, 04 Mar 2021 14:16:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614896188; cv=none; d=google.com; s=arc-20160816; b=Oa0YbD40HznvywTuqanux3+rdEO/uYCMXCluQQpPt8zAfbY2Fmy8f21X2bbvNaLrGo oGYqwz8IAkrkDITxqIuAbSrGmINHsvltJ7ssAGDn5rF1TSd+FvL4f3zBuLtIUWNaWedm RwTF8TgdYEcz4OxPJ/dsZJ8Zjr+zf8B2BLrLmZmYhEW+yn2x6fzq+Jk7e29h168yWBf3 KDGh6SlJEtRJNM+U2IIckABOzM30PDMdtM+hMSP0XFE3Es941i4c2bM9T84qnmQLCpIF voIhR+FmYvfbPLAEM+Gv4TOR5PL3ekNwijJux4v6uFaSBfNQR73yDJQW7341O0vo5KIB njKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=87e0WVkV56dpTXvqg1zPNJEnEHXGvFYDyxgC5z4r/uQ=; b=np/+O+i/UpcS+RUpGBiA0L38qnbMt5w16JZzmvPGWLrI3T8C7UhjDgnoRyusQH4op1 Bnvrc7Pq567xgjuftajEDzrqcTUxGrpaKc0KHxqT98do+Q0KsIi4L1u3VK6pDbX8HDc+ P/rwZDtWwBYGSRY/9ldDMtCs2SrFhFxmrSoiO/XLhqQJEJHY0BpmJKbN111bELZpIaF5 THs6VpZWMh9Y9VGAOZHxVR4M5NGSGFdMcCDNNRT1mWO5ZarZh+tleO6zIn4KIYWcOjS0 FLypMlfEK9d1mdIU0S6RPkN4A1y5Lk+D0WZKOA5PGkvAlgGX3YkecYJGRCfltPWh679l SClA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bi6UkkIY; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k6si527757edj.545.2021.03.04.14.16.28; Thu, 04 Mar 2021 14:16:28 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bi6UkkIY; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233718AbhCDEn3 (ORCPT + 6 others); Wed, 3 Mar 2021 23:43:29 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36742 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233573AbhCDEnK (ORCPT ); Wed, 3 Mar 2021 23:43:10 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1244gFEZ101969; Wed, 3 Mar 2021 22:42:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1614832935; bh=87e0WVkV56dpTXvqg1zPNJEnEHXGvFYDyxgC5z4r/uQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bi6UkkIYux8SYYf9jyHoOxjLkC2zYgdxiR5fat7Prm/KFC6mMGOOLn0WdlVvj0+wU otwDIVBUUy1N14OLk7ZME6DgnHOyslvOtUThPRMkMUoK2y7qknAv0iRcX1GhIxEz6O zak5/wRymiPmsJcT3MvTwak/0B7wWayTQrSfBTDk= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1244gFsU056749 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 3 Mar 2021 22:42:15 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 3 Mar 2021 22:42:15 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 3 Mar 2021 22:42:15 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1244fQfu042911; Wed, 3 Mar 2021 22:42:12 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel , Swapnil Jakhade CC: , , Lokesh Vutla Subject: [PATCH v4 13/13] phy: cadence: phy-cadence-sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Date: Thu, 4 Mar 2021 10:11:22 +0530 Message-ID: <20210304044122.15166-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210304044122.15166-1-kishon@ti.com> References: <20210304044122.15166-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 40 ++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index be2c91be4205..68d81f953f4f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -768,6 +768,40 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->input_clks[PLL0_REFCLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc: + clk_disable_unprepare(sp->input_clks[PHY_CLK]); + +err_pll_cmnlc1: + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + + return 0; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + clk_disable_unprepare(sp->input_clks[PHY_CLK]); +} + static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { @@ -848,7 +882,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) goto unregister_clk; - ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) goto unregister_clk; @@ -925,7 +959,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->input_clks[PHY_CLK]); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); unregister_clk: cdns_sierra_clk_register(sp); @@ -941,6 +975,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->apb_rst); pm_runtime_disable(&pdev->dev); + cdns_sierra_phy_disable_clocks(phy); /* * The device level resets will be put automatically. * Need to put the subnode resets here though. @@ -950,7 +985,6 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_put(phy->phys[i].lnk_rst); } - clk_disable_unprepare(phy->input_clks[PHY_CLK]); cdns_sierra_clk_unregister(phy); return 0;