From patchwork Mon Mar 8 05:37:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 395649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C847C43333 for ; Mon, 8 Mar 2021 05:38:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 644D865212 for ; Mon, 8 Mar 2021 05:38:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234464AbhCHFiS (ORCPT ); Mon, 8 Mar 2021 00:38:18 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:44691 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234436AbhCHFiC (ORCPT ); Mon, 8 Mar 2021 00:38:02 -0500 X-UUID: c7be6d2a4abc4aa294397148eb910e48-20210308 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=u3VE+kUgCgnXOQ6xrTo8ccF5dBa/h3UTVZ0nd8WVGvY=; b=V8L3ElTly1d8qWW4v47IdGYDExAe1JvocUnUi16UGTfQWltV2b6LVAr5QO34dMCaK9cMNDDsLmQEezuE9uZ5BVxmiohYSmkV6Iwt97pQeIm7IV/DTZ4etnej9BVFBOZk0rIJkeDjw9nFKamP7wRK1vTCs4rGmcUJoJx0i9NLtOE=; X-UUID: c7be6d2a4abc4aa294397148eb910e48-20210308 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1703879310; Mon, 08 Mar 2021 13:37:55 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Mar 2021 13:37:51 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 8 Mar 2021 13:37:51 +0800 From: Chunfeng Yun To: Vinod Koul , Rob Herring , Matthias Brugger CC: Chunfeng Yun , Kishon Vijay Abraham I , Greg Kroah-Hartman , Chun-Kuang Hu , Philipp Zabel , , , , , Subject: [PATCH v4 10/12] arm: dts: mt7629: harmonize node names and compatibles Date: Mon, 8 Mar 2021 13:37:43 +0800 Message-ID: <20210308053745.25697-10-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210308053745.25697-1-chunfeng.yun@mediatek.com> References: <20210308053745.25697-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 382FEC62F9FEE381406AE72691B2087CDB8F557D2AB755F1BE2B8CB43B451F6B2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is used to fix dtbs_check warning Signed-off-by: Chunfeng Yun --- v2~v4: no changes --- arch/arm/boot/dts/mt7629.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.18.0 diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi index 5cbb3d244c75..874043f0490d 100644 --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi @@ -329,8 +329,9 @@ status = "disabled"; }; - u3phy0: usb-phy@1a0c4000 { - compatible = "mediatek,generic-tphy-v2"; + u3phy0: t-phy@1a0c4000 { + compatible = "mediatek,mt7629-tphy", + "mediatek,generic-tphy-v2"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1a0c4000 0xe00>; @@ -413,14 +414,15 @@ }; }; - pciephy1: pcie-phy@1a14a000 { - compatible = "mediatek,generic-tphy-v2"; + pciephy1: t-phy@1a14a000 { + compatible = "mediatek,mt7629-tphy", + "mediatek,generic-tphy-v2"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1a14a000 0x1000>; status = "disabled"; - pcieport1: port1phy@0 { + pcieport1: pcie-phy@0 { reg = <0 0x1000>; clocks = <&clk20m>; clock-names = "ref";