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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id z1sm7412458wru.95.2021.03.12.03.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 03:39:35 -0800 (PST) From: Srinivas Kandagatla To: broonie@kernel.org, vkoul@kernel.org Cc: robh@kernel.org, devicetree@vger.kernel.org, yung-chuan.liao@linux.intel.com, pierre-louis.bossart@linux.intel.com, sanyog.r.kale@intel.com, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v3 2/5] soundwire: qcom: update port map allocation bit mask Date: Fri, 12 Mar 2021 11:39:26 +0000 Message-Id: <20210312113929.17512-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210312113929.17512-1-srinivas.kandagatla@linaro.org> References: <20210312113929.17512-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org currently the internal bitmask used for allocating ports starts with offset 0. This is bit confusing as data port numbers on Qualcomm controller are valid from 1 to 14. So adjust this bit mask accordingly, this will also help while adding static port map support. Signed-off-by: Srinivas Kandagatla --- drivers/soundwire/qcom.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.21.0 diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 6d22df01f354..9e70c53e2c7b 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -519,7 +519,7 @@ static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, port_mask = &ctrl->din_port_mask; list_for_each_entry(p_rt, &m_rt->port_list, port_node) - clear_bit(p_rt->num - 1, port_mask); + clear_bit(p_rt->num, port_mask); } mutex_unlock(&ctrl->port_lock); @@ -552,13 +552,13 @@ static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, list_for_each_entry(p_rt, &s_rt->port_list, port_node) { /* Port numbers start from 1 - 14*/ pn = find_first_zero_bit(port_mask, maxport); - if (pn > (maxport - 1)) { + if (pn > maxport) { dev_err(ctrl->dev, "All ports busy\n"); ret = -EBUSY; goto err; } set_bit(pn, port_mask); - pconfig[nports].num = pn + 1; + pconfig[nports].num = pn; pconfig[nports].ch_mask = p_rt->ch_mask; nports++; } @@ -580,7 +580,7 @@ static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, err: if (ret) { for (i = 0; i < nports; i++) - clear_bit(pconfig[i].num - 1, port_mask); + clear_bit(pconfig[i].num, port_mask); } mutex_unlock(&ctrl->port_lock); @@ -754,6 +754,9 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) ctrl->num_dout_ports = val; nports = ctrl->num_dout_ports + ctrl->num_din_ports; + /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ + set_bit(0, &ctrl->dout_port_mask); + set_bit(0, &ctrl->din_port_mask); ret = of_property_read_u8_array(np, "qcom,ports-offset1", off1, nports);