From patchwork Thu Mar 25 14:32:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 408810 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp589963jai; Thu, 25 Mar 2021 07:34:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdEcxa3kEORdaEp17XjWrU53OGFImqBLExr/xeHrbVkOpmbwc5eKy7rObFOu4e2fvsxuhx X-Received: by 2002:a17:907:2716:: with SMTP id w22mr9748326ejk.328.1616682843069; Thu, 25 Mar 2021 07:34:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616682843; cv=none; d=google.com; s=arc-20160816; b=cnCAlBJDn/UeBgcVhqhEzid/MO+jI2xS+7YFLwx0wRpGfW0QKoEq7zv6ak2/hV1bsg xgLrwpvdgG5w/HA6aRDnKmsZp2DqPq7g1vR265m2Bhx9nDs8+N08TE2I9edwsHVYDq7o +Rs3xmmlEpkD9+cg8CYaHeOvejWbyuxL2SL0cYPyhNCR34zQO9HbPJA0Nokw0Vur0JOM wipIuQEmabWKCBYry5W/tXRwozR65OT3vWouJwDvp6vMCtbs3RGyL01ArHLVomQTQzG/ l/vsbUS1+I54D+5KG1d+WY9yp39RtyjBNTCKsoG0qC9WdeT4q8L5QfQ3jE6QGY5k5jbv QR0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=CXne1FmSvQ68YcWgTLvAXeA4tLX4NYKQ5AHSLBUdayQ=; b=mJzuuUlMgacpJxwBCbsxKG6LJVhrS4bxHpA+AbXlBE64hE5OMlXmpFtJSXuKTV5Wx9 Z6BqPLQ887kcExHD7N2Zu5/gxM4J8Ypkc96VqhM6+ikIB7nBVBoD2sYXFjQpvd3FVRvS lZhPp4mfbdbJhf9ub5Gtylc7TtgnjdHCaSeTgD2AuG92gQHKOQC2wtRniDIKAutJMJIo QicE5VdAPRArGdBnny77fLUT9QmzdccAPsbtWEUJHStcW1gMJTMLc+K97LyhMlOmzb5z gfJvW51jXkeY8qiqRyzE0hZz8PhpEr7sPEoY6/G5kqUONdgw0nayi36AgJweD25J2WZx O2/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qu2si4448783ejb.373.2021.03.25.07.34.02; Thu, 25 Mar 2021 07:34:03 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231482AbhCYOda (ORCPT + 6 others); Thu, 25 Mar 2021 10:33:30 -0400 Received: from foss.arm.com ([217.140.110.172]:51006 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231499AbhCYOdJ (ORCPT ); Thu, 25 Mar 2021 10:33:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 17E0414BF; Thu, 25 Mar 2021 07:33:09 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 68E473F792; Thu, 25 Mar 2021 07:33:07 -0700 (PDT) From: Sudeep Holla To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Sudeep Holla , Trilok Soni , arve@android.com, Andrew Walbran , David Hartley , Achin Gupta , Jens Wiklander , Arunachalam Ganapathy , Marc Bonnici , Catalin Marinas , Will Deacon Subject: [PATCH v5 2/7] arm64: smccc: Add support for SMCCCv1.2 input/output registers Date: Thu, 25 Mar 2021 14:32:50 +0000 Message-Id: <20210325143255.1532452-3-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210325143255.1532452-1-sudeep.holla@arm.com> References: <20210325143255.1532452-1-sudeep.holla@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SMCCC v1.2 allows x8-x17 to be used as parameter registers and x4—x17 to be used as result registers in SMC64/HVC64. Arm Firmware Framework for Armv8-A specification makes use of x0-x7 as parameter and result registers. Current SMCCC interface in the kernel just use x0-x7 as parameter and x0-x3 as result registers. Let us add new interface to support x0-x7 as parameter and result registers. This can be extended to include x8-x17 when there are users for the same. Tested-by: Jens Wiklander Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Sudeep Holla --- arch/arm64/kernel/asm-offsets.c | 4 +++ arch/arm64/kernel/smccc-call.S | 22 +++++++++++++++ include/linux/arm-smccc.h | 50 +++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+) Hi Will/Catalin, I seemed to have missed you on these patches. I realised only when I was collecting Acks to get this series merged. The change here is simple, it would be good if you can review and ack if you are OK with it so that I can get the serier merged via ARM SoC. -- 2.25.1 diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index a36e2fc330d4..57ffea2920b8 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -132,6 +132,10 @@ int main(void) DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); + DEFINE(ARM_SMCCC_V1_2_RES_X0_OFFS, offsetof(struct arm_smccc_v1_2_res, a0)); + DEFINE(ARM_SMCCC_V1_2_RES_X2_OFFS, offsetof(struct arm_smccc_v1_2_res, a2)); + DEFINE(ARM_SMCCC_V1_2_RES_X4_OFFS, offsetof(struct arm_smccc_v1_2_res, a4)); + DEFINE(ARM_SMCCC_V1_2_RES_X6_OFFS, offsetof(struct arm_smccc_v1_2_res, a6)); BLANK(); DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address)); DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address)); diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S index d62447964ed9..0ea15c1742f3 100644 --- a/arch/arm64/kernel/smccc-call.S +++ b/arch/arm64/kernel/smccc-call.S @@ -43,3 +43,25 @@ SYM_FUNC_START(__arm_smccc_hvc) SMCCC hvc SYM_FUNC_END(__arm_smccc_hvc) EXPORT_SYMBOL(__arm_smccc_hvc) + + .macro SMCCC_v1_2 instr + .cfi_startproc + \instr #0 + ldr x8, [sp] + stp x0, x1, [x8, #ARM_SMCCC_V1_2_RES_X0_OFFS] + stp x2, x3, [x8, #ARM_SMCCC_V1_2_RES_X2_OFFS] + stp x4, x5, [x8, #ARM_SMCCC_V1_2_RES_X4_OFFS] + stp x6, x7, [x8, #ARM_SMCCC_V1_2_RES_X6_OFFS] + ret + .cfi_endproc +.endm + +SYM_FUNC_START(arm_smccc_v1_2_hvc) + SMCCC_v1_2 hvc +SYM_FUNC_END(arm_smccc_v1_2_hvc) +EXPORT_SYMBOL(arm_smccc_v1_2_hvc) + +SYM_FUNC_START(arm_smccc_v1_2_smc) + SMCCC_v1_2 smc +SYM_FUNC_END(arm_smccc_v1_2_smc) +EXPORT_SYMBOL(arm_smccc_v1_2_smc) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 62c54234576c..0b8fa285a054 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -186,6 +186,56 @@ struct arm_smccc_res { unsigned long a3; }; +#ifdef CONFIG_ARM64 +/* TODO Need to implement for ARM too */ +/** + * struct arm_smccc_v1_2_res - Result from SMC/HVC call + * @a0-a7 result values from registers 0 to 7 + */ +struct arm_smccc_v1_2_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; +}; + +/** + * arm_smccc_v1_2_hvc() - make HVC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 7 + * + * This function is used to make HVC calls following SMC Calling Convention + * v1.2 or above. The content of the supplied param are copied to registers + * 0 to 7 prior to the HVC instruction. The return values are updated with + * the content from register 0 to 7 on return from the HVC instruction. + */ +asmlinkage +void arm_smccc_v1_2_hvc(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_v1_2_res *res); + +/** + * arm_smccc_v1_2_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 7 + * + * This function is used to make SMC calls following SMC Calling Convention + * v1.2 or above. The content of the supplied param are copied to registers + * 0 to 7 prior to the SMC instruction. The return values are updated with + * the content from register 0 to 7 on return from the SMC instruction. + */ +asmlinkage +void arm_smccc_v1_2_smc(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm_smccc_v1_2_res *res); +#endif + /** * struct arm_smccc_quirk - Contains quirk information * @id: quirk identification