From patchwork Sat Apr 10 09:11:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 419357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3C6BC433ED for ; Sat, 10 Apr 2021 09:14:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8EA3C61165 for ; Sat, 10 Apr 2021 09:14:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234478AbhDJJOc (ORCPT ); Sat, 10 Apr 2021 05:14:32 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34947 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234638AbhDJJOa (ORCPT ); Sat, 10 Apr 2021 05:14:30 -0400 X-UUID: 0f10d46826bd45648aa8edd615321d3f-20210410 X-UUID: 0f10d46826bd45648aa8edd615321d3f-20210410 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 648754173; Sat, 10 Apr 2021 17:14:13 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 10 Apr 2021 17:14:11 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 10 Apr 2021 17:14:10 +0800 From: Yong Wu To: Matthias Brugger , Joerg Roedel , Rob Herring , Krzysztof Kozlowski CC: Evan Green , Robin Murphy , Tomasz Figa , Will Deacon , , , , , , , , , Nicolas Boichat , Matthias Kaehlcke , , , , , , Subject: [PATCH v5 15/16] arm: dts: mediatek: Get rid of mediatek, larb for MM nodes Date: Sat, 10 Apr 2021 17:11:27 +0800 Message-ID: <20210410091128.31823-16-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210410091128.31823-1-yong.wu@mediatek.com> References: <20210410091128.31823-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org After adding device_link between the IOMMU consumer and smi, the mediatek,larb is unnecessary now. CC: Matthias Brugger Signed-off-by: Yong Wu Reviewed-by: Evan Green --- arch/arm/boot/dts/mt2701.dtsi | 2 -- arch/arm/boot/dts/mt7623n.dtsi | 5 ----- 2 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index fade14284017..0a7892bcf536 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -564,7 +564,6 @@ clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -577,7 +576,6 @@ clocks = <&imgsys CLK_IMG_VENC>; clock-names = "jpgenc"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; }; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi index 1880ac9e32cf..2e6c16164744 100644 --- a/arch/arm/boot/dts/mt7623n.dtsi +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -121,7 +121,6 @@ clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -144,7 +143,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_OVL>; iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; - mediatek,larb = <&larb0>; }; rdma0: rdma@14008000 { @@ -154,7 +152,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_RDMA>; iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; - mediatek,larb = <&larb0>; }; wdma@14009000 { @@ -164,7 +161,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_WDMA>; iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; - mediatek,larb = <&larb0>; }; bls: pwm@1400a000 { @@ -215,7 +211,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb0>; }; dpi0: dpi@14014000 {