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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 04/17] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Date: Thu, 6 May 2021 03:07:18 +0530 Message-Id: <20210505213731.538612-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add 'interconnects' and 'interconnect-names' to the device-tree binding documentation for qcom crypto IP. These properties describe the interconnect path between crypto and main memory and the interconnect type respectively. While at it also move 'clocks' to the optional properties sections, as crypto IPs on SoCs like sm8150, sm8250, sm8350 (and so on), don't require linux to setup the clocks (this is already done by the secure firmware running before linux). Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/crypto/qcom-qce.txt | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt index 07ee1b12000b..3f70cee1a491 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt @@ -4,15 +4,19 @@ Required properties: - compatible : should be "qcom,crypto-v5.1" - reg : specifies base physical address and size of the registers map -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "iface" clocks register interface - "bus" clocks data transfer interface - "core" clocks rest of the crypto block - dmas : DMA specifiers for tx and rx dma channels. For more see Documentation/devicetree/bindings/dma/dma.txt - dma-names : DMA request names should be "rx" and "tx" - iommus : phandle to apps_smmu node with sid mask +Optional properties: +- clocks : phandle to clock-controller plus clock-specifier pair +- clock-names : "iface" clocks register interface + "bus" clocks data transfer interface + "core" clocks rest of the crypto block +- interconnects : Interconnect path between qce crypto and main memory +- interconnect-names: should be "memory" + Example: crypto@fd45a000 { compatible = "qcom,crypto-v5.1"; @@ -23,4 +27,6 @@ Example: clock-names = "iface", "bus", "core"; dmas = <&cryptobam 2>, <&cryptobam 3>; dma-names = "rx", "tx"; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; };