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Sat, 22 May 2021 13:10:24 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org, agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ping.bai@nxp.com, frieder.schrempf@kontron.de, aford173@gmail.com, abel.vesa@nxp.com, Peng Fan , Rob Herring Subject: [PATCH V6 2/4] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL Date: Sat, 22 May 2021 21:42:47 +0800 Message-Id: <20210522134249.15322-3-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210522134249.15322-1-peng.fan@oss.nxp.com> References: <20210522134249.15322-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR04CA0155.apcprd04.prod.outlook.com (2603:1096:4::17) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR04CA0155.apcprd04.prod.outlook.com (2603:1096:4::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.23 via Frontend Transport; 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Each BLK CTL have different power domain inputs and they have different names, so we are not able to list all the power domain names for each BLK CTL here. For example: i.MX8MM dispmix BLK CTL, it has power-domains = <&pgc_dispmix>, <&pgc_mipi>; power-domain-names = "dispmix", "mipi"; vpumix BLK CTL, it has power-domains = <&vpumix_pd>, <&vpu_g1_pd>, <&vpu_g2_pd>, <&vpu_h1_pd>; power-domain-names = "vpumix", "g1", "g2", "h1"; Reviewed-by: Rob Herring Signed-off-by: Peng Fan --- .../bindings/soc/imx/fsl,imx-blk-ctl.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml -- 2.30.0 diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml new file mode 100644 index 000000000000..a66f11acc6b4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTL + +maintainers: + - Peng Fan + +description: + i.MX BLK_CTL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. It usually contains + clocks and resets amongst other things. Here we take the clocks + and resets as virtual PDs, the reason we could not take it as + clock provider is there is A/B lock issue between power domain + and clock. + +properties: + compatible: + items: + - enum: + - fsl,imx8mm-dispmix-blk-ctl + - fsl,imx8mm-vpumix-blk-ctl + - const: syscon + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 1 + + power-domains: + minItems: 1 + maxItems: 32 + + power-domain-names: + minItems: 1 + maxItems: 32 + + clocks: + minItems: 1 + maxItems: 32 + +required: + - compatible + - reg + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + + dispmix_blk_ctl: blk-ctl@32e28000 { + compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon"; + reg = <0x32e28000 0x100>; + #power-domain-cells = <1>; + power-domains = <&pgc_dispmix>, <&pgc_mipi>; + power-domain-names = "dispmix", "mipi"; + clocks = <&clk IMX8MM_CLK_DISP_ROOT>, <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + };