From patchwork Tue Jun 15 17:32:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC96AC49EA2 for ; Tue, 15 Jun 2021 17:33:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6BD161403 for ; Tue, 15 Jun 2021 17:33:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231479AbhFORfM (ORCPT ); Tue, 15 Jun 2021 13:35:12 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35307 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231289AbhFORe7 (ORCPT ); Tue, 15 Jun 2021 13:34:59 -0400 X-UUID: 558b68876c8e450e9b7d3a41ff547240-20210616 X-UUID: 558b68876c8e450e9b7d3a41ff547240-20210616 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 789805714; Wed, 16 Jun 2021 01:32:47 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:46 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jitao Shi Subject: [PATCH 22/27] arm64: dts: mt8195: add edp nodes Date: Wed, 16 Jun 2021 01:32:28 +0800 Message-ID: <20210615173233.26682-22-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jitao Shi add edp nodes for mt8195 Signed-off-by: Jitao Shi --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 59 +++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 256818c4c0bf..d7d2c2a8f461 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -23,6 +23,8 @@ aliases { dpi1 = &disp_dpi1; + dp-intf0 = &dp_intf0; + dp-intf1 = &dp_intf1; }; clocks { @@ -1155,6 +1157,29 @@ status = "disabled"; }; + disp_pwm0: disp_pwm0@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM0_SEL>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + disp_pwm1: disp_pwm1@1100f000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM1_SEL>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; + clock-names = "main", "mm"; + status = "disabled"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -2397,6 +2422,30 @@ status = "disabled"; }; + dp_intf1: dp_intf1@1c113000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&topckgen CLK_TOP_DP_SEL>, + <&topckgen CLK_TOP_TVDPLL2_D2>, + <&topckgen CLK_TOP_TVDPLL2_D4>, + <&topckgen CLK_TOP_TVDPLL2_D8>, + <&topckgen CLK_TOP_TVDPLL2_D16>, + <&topckgen CLK_TOP_TVDPLL2>; + clock-names = "hf_fmm_ck", + "hf_fdp_ck", + "MUX_DP", + "TVDPLL_D2", + "TVDPLL_D4", + "TVDPLL_D8", + "TVDPLL_D16", + "DPI_CK"; + status = "disabled"; + }; + hdmi0: hdmi@1c300000 { compatible = "mediatek,mt8195-hdmi"; reg = <0 0x1c300000 0 0x1000>; @@ -2421,11 +2470,19 @@ edp_tx: edp_tx@1c500000 { status = "disabled"; - compatible = "mediatek,mt8195-dp_tx"; + compatible = "mediatek,mt8195-edp_tx"; reg = <0 0x1c500000 0 0x8000>; power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; interrupts = ; }; + + dp_tx: dp_tx@1c600000 { + compatible = "mediatek,mt8195-dp_tx"; + reg = <0 0x1c600000 0 0x8000>; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = ; + status = "disabled"; + }; }; hdmiddc0: ddc_i2c {