From patchwork Thu Jun 17 19:09:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 463270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0864C49EA5 for ; Thu, 17 Jun 2021 19:09:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A97D8613EC for ; Thu, 17 Jun 2021 19:09:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233080AbhFQTLg (ORCPT ); Thu, 17 Jun 2021 15:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233085AbhFQTLa (ORCPT ); Thu, 17 Jun 2021 15:11:30 -0400 Received: from mail.bugwerft.de (mail.bugwerft.de [IPv6:2a03:6000:1011::59]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9F1C3C061760; Thu, 17 Jun 2021 12:09:22 -0700 (PDT) Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id 6916A4C009A; Thu, 17 Jun 2021 19:09:21 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 8/9] clk: cs2000-cp: freeze config during register fiddling Date: Thu, 17 Jun 2021 21:09:11 +0200 Message-Id: <20210617190912.262809-9-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Make sure to freeze the configuration of the chip during the programming of 32-bit registers. This avoids the processing of invalid intermediate states. Signed-off-by: Daniel Mack --- drivers/clk/clk-cs2000-cp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index f3093d99c639..a630fb75bd4c 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -52,6 +52,7 @@ #define FRACNSRC_DYNAMIC (1 << 0) /* GLOBAL_CFG */ +#define FREEZE (1 << 7) #define ENDEV2 (0x1) /* FUNC_CFG1 */ @@ -336,6 +337,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, FREEZE); + if (ret < 0) + return ret; + ret = cs2000_select_ratio_mode(priv, rate, parent_rate); if (ret < 0) return ret; @@ -348,6 +353,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, if (ret < 0) return ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, 0); + if (ret < 0) + return ret; + priv->saved_rate = rate; priv->saved_parent_rate = parent_rate;