From patchwork Fri Aug 13 06:53:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 497210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0228C4338F for ; Fri, 13 Aug 2021 06:54:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B4B1A60FC4 for ; Fri, 13 Aug 2021 06:54:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238763AbhHMGzY (ORCPT ); Fri, 13 Aug 2021 02:55:24 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:36600 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238879AbhHMGzV (ORCPT ); Fri, 13 Aug 2021 02:55:21 -0400 X-UUID: 72f64193c7e24027af1f8e318f8a8fde-20210813 X-UUID: 72f64193c7e24027af1f8e318f8a8fde-20210813 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1478555678; Fri, 13 Aug 2021 14:54:52 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 13 Aug 2021 14:54:50 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 13 Aug 2021 14:54:49 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , Matthias Brugger , Will Deacon , Robin Murphy CC: Krzysztof Kozlowski , Evan Green , Tomasz Figa , Tomasz Figa , , , , , , , , , Nicolas Boichat , , Subject: [PATCH v2 09/29] iommu/mediatek: Add tlb_lock in tlb_flush_all Date: Fri, 13 Aug 2021 14:53:04 +0800 Message-ID: <20210813065324.29220-10-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210813065324.29220-1-yong.wu@mediatek.com> References: <20210813065324.29220-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The tlb_flush_all also touches the registers about tlb operations. Add spinlock in it to protect the tlb registers. If flush_all is called from tlb_flush_range, then no need this spinlock as tlb_flush_range already hold the tlb_lock. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 1e18fff76e61..d64139ab59d0 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -205,15 +205,24 @@ static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) return container_of(dom, struct mtk_iommu_domain, domain); } -static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) +static void __mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) { - if (pm_runtime_get_if_in_use(data->dev) <= 0) - return; - writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + data->plat_data->inv_sel_reg); writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); wmb(); /* Make sure the tlb flush all done */ +} + +static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) +{ + unsigned long flags; + + if (pm_runtime_get_if_in_use(data->dev) <= 0) + return; + + spin_lock_irqsave(&data->tlb_lock, flags); + __mtk_iommu_tlb_flush_all(data); + spin_unlock_irqrestore(&data->tlb_lock, flags); pm_runtime_put(data->dev); } @@ -251,7 +260,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, if (ret) { dev_warn(data->dev, "Partial TLB flush timed out, falling back to full flush\n"); - mtk_iommu_tlb_flush_all(data); + __mtk_iommu_tlb_flush_all(data); } /* Clear the CPE status */ writel_relaxed(0, data->base + REG_MMU_CPE_DONE);