From patchwork Fri Dec 24 20:09:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 528394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF657C433FE for ; Fri, 24 Dec 2021 20:10:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353635AbhLXUKK (ORCPT ); Fri, 24 Dec 2021 15:10:10 -0500 Received: from mout.gmx.net ([212.227.15.18]:46385 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353566AbhLXUKC (ORCPT ); Fri, 24 Dec 2021 15:10:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1640376594; bh=xgXOvOiI5djkt9bgMVQwlcwa+uldX2qpAJfM9bdL9Dk=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=eW8U6CGS/A39+2N3r17jp1rd8k/Soa3C42l4bgi8ddg/dSIwUGK2sXBhNW0/I+iox K34UB8lhSiq3hjiBoWRx9a4l2CouE8TzH4xY3hhn6SI8WDzQU/flKSLs4Tw+zyAKbS baPu33Km2YzR0g/b+vi12LjSKvlsxUBpwbCtZMUI= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M7sDg-1n4ilU1PZy-0053e0; Fri, 24 Dec 2021 21:09:54 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, Andy Shevchenko , Avi Fishman , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH v3 4/9] dt-bindings: pinctrl: Add Nuvoton WPCM450 Date: Fri, 24 Dec 2021 21:09:30 +0100 Message-Id: <20211224200935.93817-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211224200935.93817-1-j.neuschaefer@gmx.net> References: <20211224200935.93817-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:jNQWeymtJVy6MUZXGKffNUHgUkUWkDV45wh7rG8QpjZRI7gRyz5 +QM4XZwnMPW9VKkAwgnOZKQsc7tFCvlJ+GBiY9bCEx/3bJd3lyXe4+RvNNaBWSn3c3qc3uj YOinzF0LXh4EiTo52UiW+mFbexNxUUeQDSrdL1yw6Vij+oRYFugZoxMOSchn+vnQOj80W8N lp0a0hYpetET5r9EvGpnw== X-UI-Out-Filterresults: notjunk:1;V03:K0:WVy6bPb/yBA=:hUikcXEA4vZWNW/yTiufbz MhpQYNJSpPoujuc9taQMDvjOzscgrPptHHUHppr+1jXV5ZPSuTra2e23TjDaRT9h20dV6geba 54lkitkGfxJswUN1lwUKWXhnFgn8yUzVe8Nsg6LIweqGpkO7Uv+CwWVHToHUqK5oLjaTYPuZ4 AmaWHxyZkl0v1KMyxHHcunj65GoH1Ut/4dHywyOTQ872s6AQRRudoK+aeSx0Mj+nnNr5ylNRt T6TPUpSVkZLqKePQEFjU9uFbQeTcpogSro+DiTQ1dUE+2p+p6XUVzz6wI6CF5D7nu4sL8pVw8 UWwSAKAmtfGKREmG5i1JAdpcxpcsvxaNdnOGhFAiPhVfYFMOw3KbUShIID0d2mjBdV4u9qWDM H7zIKrt78jak8BaeDF3c02aglABn86TWHpblDla86C3/2uCeXmM1TrAvws61hH1Sg/Q0SWfrg hDoCUZ3eHoNCzE2+9Pm2LbvpyV9So4kPXM+TNNhJWoQ2GyHxo81m9DErCTCH1858iiQjEj5ow Nkcz75UcniscotpGXbaa1nuBXtnOF0xpQWTqd6xufM2zxkbz5m+uqhoNSfyQ4fuwDuUpAOcJ4 ZbWXdphB7VuZ41UXxNa8Cr1+GMDlWJkkqhWka8p+xDi4/3oybYZVPOeyBR9D6lJxCkQK9XcdH z0v+ajbEJ+z+avVd55ErGa23r+KEQM3QWDTsiy0EBFFYKcyh66ysP0MYnkaoFWIuBcl9c3p10 vFyZVcdpMH4m3wZd0aAJuby1Erb0vC9tjd8QDbj2AG9B9kZESsuTCQV9okcFIfl/PiN3Qaslq FANvad285E3mFsPyy1BCltb+jlJYhLUN9hoozcklRHNmlts4K99OLAnH8oLzzL9fpkpigtYUq xpN5Dqe2nptf4PLNOdvm5816nUIBVU/vPQjHLKVCBYRE6S2xvx79XMcyUTKdo7Y4ULazCcEGl g3yUJE9x7GkW9yYNnr/EkK54rVSMHP5qbkTAuKTF7N5WvZCGhg/e5VegGc1LnRBZZFN7SzIMe mJ5FdRkcR0tu9EYmz5U0V/x/qTOZp2YtoUQ8p1M+TYOBKfvPn2kMQaKlhtFIfz9zW7XNzzBWP BIgTHpPcOyg41s= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This binding is heavily based on the one for NPCM7xx, because the hardware is similar. There are some notable differences, however: - The addresses of GPIO banks are not physical addresses but simple indices (0 to 7), because the GPIO registers are not laid out in convenient blocks. - Pinmux settings can explicitly specify that the GPIO mode is used. Certain pins support blink patterns in hardware. This is currently not modelled in the DT binding. Signed-off-by: Jonathan Neuschäfer --- v3: - Make changes suggested by Rob Herring - Fix lint errors - Simplify child node patterns - Remove if/type=object/then trick - Reduce interrupts.maxItems to 3: 4 aren't necessary - Replace list of gpio0/1/2/etc. with pattern - Remove nuvoton,interrupt-map again, to simplify the binding - Make tuples clearer v2: - https://lore.kernel.org/lkml/20211207210823.1975632-5-j.neuschaefer@gmx.net/ - Move GPIO into subnodes - Improve use of quotes - Remove unnecessary minItems/maxItems lines - Remove "phandle: true" - Use separate prefixes for pinmux and pincfg nodes - Add nuvoton,interrupt-map property - Make it possible to set pinmux to GPIO explicitly v1: - https://lore.kernel.org/lkml/20210602120329.2444672-5-j.neuschaefer@gmx.net/ --- .../pinctrl/nuvoton,wpcm450-pinctrl.yaml | 159 ++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 0000000000000..2d15737b5815e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer + +properties: + compatible: + const: nuvoton,wpcm450-pinctrl + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + # There are three kinds of subnodes: + # 1. a GPIO controller node for each GPIO bank + # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 3. a pinconf node configures properties of a single pin + + "^gpio": + type: object + + description: + Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18 + GPIOs. Some GPIOs support interrupts. + + properties: + reg: + description: GPIO bank number (0-7) + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 3 + description: + The interrupts associated with this GPIO bank + + required: + - reg + - gpio-controller + - '#gpio-cells' + + "^mux-": + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7, gpio ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + "^cfg-": + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + pattern: "^gpio1?[0-9]{1,2}$" + + input-debounce: true + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinmux_uid: mux-uid { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + pinctrl_uid: cfg-uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + };